- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384004 > TLC34058-110M (Texas Instruments, Inc.) 256 ?24 COLOR PALETTE PDF資料下載
參數(shù)資料
| 型號： | TLC34058-110M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 256 ?24 COLOR PALETTE |
| 中文描述： | 256？24調(diào)色板 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 322K |
| 代理商： | TLC34058-110M |
TLC34058-110M
256
×
24 COLOR PALETTE
SGLS075 – JANUARY 1994
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PRINCIPLES OF OPERATION
control-register write/read
The four control registers are addressed with internal-address-register values 04–07. On writing to or reading
from the internal-address register, the additional address bits ADDRab are automatically reset to 0. To facilitate
read-modify-write operations, the internal-address register does not increment after writing to or reading from
the control registers. All control registers may be accessed at any time. When accessing the control registers,
C0 and C1 are respectively set low and high. Refer to Table 3 for a quick reference.
Table 3. Writing to or Reading From Control Registers
R/W
C1
C0
ADDRba
ADDRab
FUNCTION
L
L
L
X
X
Write ADDR0–ADDR7: D0–D7
→
ADDR0–ADDR7; 0
→
ADDRa,b
Write control register: D0–D7
→
control register
Read ADDR0–ADDR7: ADDR0–ADDR7
→
D0–D7; 0
→
ADDRa,b
Read control register: control register
→
D0–D7
L
H
L
L
L
H
L
L
X
X
H
H
L
L
L
X = irrelevant
summary of internal-address-register operations
Table 4 provides a summary of operations that use the internal-address register. Figure 1 presents the read/write
timing for the device. If an invalid address is loaded into the internal-address register, the device ignores
subsequent data from the MPU during a write operation and sends incorrect data to the MPU during a read
operation.
Table 4. Internal-Address-Register Operations
INTERNAL-ADDRESS-
REGISTER VALUE
(ADDR0–ADDR7) (HEX)
C1
C0
MPU ACCESS
ADDRab
(COUNTS
MODULO 3)
00
01
11
00
01
110
COLOR
Red value
Green value
Blue value
Red value
Green value
Blue value
00–FF
L
H
Color-palette RAM
00–03
H
H
Over color 0 to 3
04
05
06
07
H
H
H
H
L
L
L
L
Read-mask register
Blink-mask register
Command register
Test register
interruption of display-refresh pixel data (via simultaneous pixel-data retrieval and MPU write)
If the MPU is writing to a particular palette-RAM location or overlay register (during the blue cycle) and the
display-refresh process is accessing pixel data from the same RAM location or overlay register, one or more
pixels on the display screen may be disturbed. If the MPU write data is valid during the complete chip-enable
period, a maximum of one pixel is disturbed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC354MD | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS |
| TLC354MN | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS |
| TLC354PW | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS |
| TLC354Y | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS |
| TLC354D | LinCMOSE QUADRUPLE DIFFERENTIAL COMPARATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34058-110MGA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 x 24 COLOR PALETTE |
| TLC34058-110MGAB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 ?? 24 COLOR PALETTE |
| TLC34058-110MHFG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 x 24 COLOR PALETTE |
| TLC34058-135FN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 ?? 24 COLOR PALETTE |
| TLC34058-80FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。