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參數(shù)資料
| 型號： | TLC34058-110M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 256 ?24 COLOR PALETTE |
| 中文描述： | 256？24調(diào)色板 |
| 文件頁數(shù)： | 14/21頁 |
| 文件大?。?/td> | 322K |
| 代理商： | TLC34058-110M |
TLC34058-110M
256
×
24 COLOR PALETTE
SGLS075 – JANUARY 1994
14
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
PRINCIPLES OF OPERATION
microprocessor-unit (MPU) interface
As shown in the functional block diagram, the MPU has direct access to the internal control registers and color
overlay palettes via a standard MPU interface. Since the palette-RAM and overlay registers have dual ports,
they can be updated without affecting the display refresh process. One port is allocated for updating or reading
data and the other for display.
palette-RAM write or read
The palette-RAM location is addressed by the internal 8-bit address register (ADDR0–ADDR7). The MPU can
either write to or read from this register. The register eliminates the need for external address multiplexers.
ADDR0–ADDR7 are updated via D0–D7. To address the red, green, and blue part of a particular RAM location,
the internal address register is provided with two additional bits, ADDRa and ADDRb. These address bits count
modulo 3 and are reset to 0 when the MPU accesses the internal-address register.
After writing to or reading from the internal-address register, the MPU executes three write or read cycles (red,
green, and blue). The register ADDRab is incremented after each of these cycles so that the red, green, and
blue information is addressed from the correct part of the particular RAM location. During the blue write cycle,
the red, green, and blue color information is adjoined to form a 24-bit word, which is then written to the particular
RAM location. After the blue write/read cycle, the internal address register bits ADDR0–ADDR7 are
incremented to access the next RAM location. For an entire palette-RAM write or read, the bits ADDR0–ADDR7
are reset to 00 after accessing the FF (256) palette-RAM location.
Two additional control bits, C0 and C1, are used to differentiate the palette-RAM read/write function from other
operations that utilize the internal-address register. C0 and C1 are respectively set high and low for writing to
or reading from the palette RAM. Table 1 summarizes this differentiation, along with other internal-
address-register operations. C0 and C1 are each set low for writing to or reading from the internal-address
register.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC34058-110MGA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 x 24 COLOR PALETTE |
| TLC34058-110MGAB | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 ?? 24 COLOR PALETTE |
| TLC34058-110MHFG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 x 24 COLOR PALETTE |
| TLC34058-135FN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:256 ?? 24 COLOR PALETTE |
| TLC34058-80FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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