參數(shù)資料
型號： TLC320AD50CPTR
廠商： TEXAS INSTRUMENTS INC
元件分類： 模擬信號調理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP48
封裝： PLASTIC, QFP-48
文件頁數(shù)： 41/56頁
文件大?。?/td> 555K
代理商： TLC320AD50CPTR
6–1
6 Register Set
Bits D12 through D8 in a secondary serial communication comprise the address of the register that is written with
data carried in D7 through D0. D13 determines a read or write cycle to the addressed register. When low, a write cycle
is selected.
The following table shows the register map.
Table 6–1. Register Map
REGISTER NO.
D15
D14
D13
D12
D11
D10
D9
D8
REGISTER NAME
0
No operation
1
0
1
Control 1
2
0
1
0
Control 2
3
0
1
Control 3
4
0
1
0
Control 4
6.1
Control Register 1
Table 6–2. Control Register 1
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
1
–
Software reset
0
–
Software reset not asserted
–
1
–
Software power down (analog and filters)
–
0
–
Software power down (not asserted)
–
1
–
Select AUXP and AUXM for ADC
–
0
–
Select INP and INM for ADC
–
0
–
Select INP and INM for monitor
–
1
–
Select AUXP and AUXM for monitor
–
1
–
Monitor amplifier gain = – 18 dB (see Note 1)
–
1
0
–
Monitor amplifier gain = – 8 dB (see Note 1)
–
0
1
–
Monitor amplifier gain = 0 dB (see Note 1)
–
0
–
Monitor amp mute
–
1
–
Digital loopback asserted
–
0
–
Digital loopback not asserted
–
1
16-bit DAC mode (hardware secondary requests)
–
0
Not 16-bit DAC mode (software secondary requests) [(15+1)– bit mode]
Default value: 0 0 0 0 0 0 0 0
NOTE 1: These gains are for a single-ended input. The gain is 6 dB lower with a differential input.
A software reset is a one-shot operation and this bit is cleared to 0 after reset. It is not necessary to write a 0 to end
the master reset operation. Writing 0s to the reserved bits is suggested.
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