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參數(shù)資料
| 型號： | TLC2932AIPWR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PHASE LOCKED LOOP, 38 MHz, PDSO14 |
| 封裝： | GREEN, PLASTIC, TSSOP-14 |
| 文件頁數(shù)： | 20/23頁 |
| 文件大小： | 531K |
| 代理商： | TLC2932AIPWR |
TLC2932A
HIGH PERFORMANCE PHASE LOCKED LOOP
SLES150 OCTOBER 2005
6
TI.COM
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
electrical characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted) (continued)
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High level output voltage
IOH = –2 mA
2.4
V
VOL
Low level output voltage
IOL = 2 mA
0.3
V
IOZ
High impedance state output current
PFD inhibit = high, VO = VDD or GND
±1
A
VIH
High level input voltage at FinA, FinB
2.1
V
VIL
Low level input voltage at FinA, FinB
0.5
V
VTH
Input threshold voltage at PFD inhibit
0.9
1.5
2.1
CIN
Input capacitance at FinA, FinB
5.6
pF
ZIN
Input impedance at FinA, FinB
10
M
IDD(Z)
High impedance state PFD supply current
See Note 6
1
A
IDD(PFD)
PFD supply current
See Note 7
3
mA
NOTES:
6. The current into LOGIC VDD when FINA and FINB = ground, PFD INHIBIT = VDD, PFD OUT open, and VCO OUT is inhibited.
7. The current into LOGIC VDD when FINA = 1 MHz and FINB = 1 MHz (VI(PP) = 3 V, rectangular wave), PFD INHIBIT = GND, PFD
OUT open, and VCO OUT is inhibited.
operation characteristics, VDD = 3 V, TA = 25°C (unless otherwise noted)
VCO section
Parameter
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fOSC
Operation oscillation frequency
RBIAS = 3.3 k, VCO IN = 1/2 VDD
17
25
33
MHz
fSTB
Time to stable oscillation (see Note 8)
10
s
tr
Rise time
CL = 15 pF
9
14
ns
tf
Fall time
CL = 15 pF
7.6
12
ns
Duty cycle at VCO OUT
RBIAS = 3.3 k, VCO IN = 1/2 VDD
45%
50%
55%
α (fOSC) Temperature coefficient of oscillation
frequency
VCO IN = 1/2 VDD, TA = –20°C to
75
°C
–0.264
%/
°C
kSVS
(fosc)
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 VDD, VDD = 4.75 V to
5.25 V
0.004
%/mV
Jitter absolute (see Note 9)
PLL jitter, N = 128
325
ps
NOTES:
8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fmax
Maximum operation frequency
17
MH
tPLZ
PFD output disable time from low level
22
50
ns
tPHZ
PFD output disable time from high level
21
50
ns
tPZL
PFD output enable time to low level
6.5
30
ns
tPZH
PFD output enable time to high level
7
30
ns
tr
Rise time
CL = 15 pF
3.4
10
ns
tf
Fall time
CL = 15 pF
1.9
10
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC2932AIPWRG4 | 功能描述:鎖相環(huán) - PLL Phase-Locked Loop Systems RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2932EVM | 制造商:Texas Instruments 功能描述:PHASE-LOCK LOOP EVALUATION MODULE - Bulk |
| TLC2932IPW | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2932IPWG4 | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| TLC2932IPWR | 功能描述:鎖相環(huán) - PLL PHASE LOCKED LOOP RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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