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參數(shù)資料
| 型號： | TFDS6502E-TR3 |
| 廠商： | VISHAY SEMICONDUCTORS |
| 元件分類： | 其它接口 |
| 英文描述： | SPECIALTY INTERFACE CIRCUIT, XMA8 |
| 封裝： | 13 X 5.95 X 5.30 MM, SIDE VIEW-8 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 690K |
| 代理商： | TFDS6502E-TR3 |
TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E
Vishay Semiconductor
Rev. B1.6, 02–Nov–00
11
www.vishay.com
Document Number 82526
11.8
5.08
2.54
5
876
1.8
0.63
1.1
1.0
0.63
1
8.3
2.2
4
12
3
2.54
5.08
15069
Figure 9. TFDS6502E Side View Package
Pad 1 is longer to designate Pin 1 connection to transceiver.
1.27
0.8
18
8.89
1.8
15068
Figure 10. TFDT6502E Top View Package
Pad 1 is longer to designate Pin 1 connection to transceiver.
Note: Leads of the device should be at least 0.3 mm within the ends of the pads.
Recommended Solder Profile
Time ( s )
T
emperature
(
C
)
14874
°
0
30
60
90
120
150
180
210
240
0
50
100
150
200
250
300
350
2 - 4
°C/s
10 s max.
@ 230
°C
90 s max.
120 - 180 s
2 - 4
°C/s
Figure 11. Recommended Solder Profile
Current Derating Diagram
0
100
200
300
400
500
600
–40 –20
0
20
40
60
80 100 120 140
Peak
Operating
Current
(
mA
)
Temperature (
°C )
14875
Current derating as a function of
the maximum forward current of
IRED. Maximum duty cycle: 25%.
Figure 12. Current Derating Diagram
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