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參數(shù)資料
| 型號： | TEA2028 |
| 廠商： | 意法半導體 |
| 英文描述： | APPLICATION NOTE |
| 中文描述： | 應(yīng)用筆記 |
| 文件頁數(shù)： | 22/47頁 |
| 文件大?。?/td> | 532K |
| 代理商： | TEA2028 |
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A. BLOCKDIAGRAM
”V’
OUT
” will set the flip-flop thereby allowing the
capacitor ”C1” to be charged by current ”I
C
” deliv-
ered throughcurrentgenerator.Thevoltageacross
capacitor begins rising until it reaches ”V
REF
”. At
this time,comparator ”C” is triggered,the outputof
which will in turn reset the flip-flop. The capacitor
”C” is consequentlydischargedby current I
D
- I
C
.
1
&
≥
1
S
R
Q
Q
V
REF
C1
V
1
+
I
C
144
μ
A
I
380
μ
A
16
μ
s
AS
Auto-Set
Signal
V
10
To Output
Stage
t’
OUT
T
10
t’
OUT
V’
OUT
Window
C
2
Figure42
B. T10CALCULATION (see Figure 43)
T
10
=C1
V
1
I
C
=C1
V
REF
I
C
”I
C
” is a fraction of ”I
REF
” on pin 14
I
C
=I
REF
α
T
10
=
α
R14
C1 = 2.64
R14
C1
with R14 = 3.32k
, C1= 3.3nF
T
10
= 29
μ
s
- T
10
is independentfrom temperatureand V
CC
-
α
hasamaximumdispersionof
±
3%from device
to device
=
V
REF
α
μ
A
C. 16
μ
s WINDOW
This window is generatedby the line logic circuitry
and sets the maximum phase variations of the
output signal ”V
10
”.
Also, for protectionpurposes, should”V
16
” voltage
equal ”0”, the output signal will be alwayspresent
and have a maximum phase shift of 16
μ
s with
respect to the falling-edge of the line saw-tooth.
D. AUTO-SET TO ”1”
To provide protection, this function will trigger the
flip-flop if the modulator is disabled, i.e.
V
16
> V
13(MAX)
.
Maximum
Phase
Variation
t
V
REF
(1.26V)
0
V’
V
OUT
1
4
μ
s
Auto-Set
Set
Window
16
μ
s
16
μ
s
T
10
T
10
T
10
V
10
2
Figure 43
E. MAXIMUM ”T10” VALUE AS AFUNCTION
OF”C1”
T
10 (Min.)
: 16
μ
s (window) + 4
μ
s (auto set) = 20
μ
s
C1
(Min.)
= 2.3nF
T
10 (Max.)
: forC1
V
REF
I
D
I
C
T
10 (Max.)
= 40
μ
s
C1
(Max.)
= 4.6nF
+C1
V
REF
I
C
≤
64
μ
s
For normal operation, C1 value has to be chosen
between2.3nF and 4.6nF.
If Pin 1 is grounded, output signal (Pin 10) is
inhibited andgoes high.
V.5.2.5 - Line output stage & inhibitions
≥
1
10
6
12
I
V
R
T
10
10
CC
L
+
Output
To
Line ”DRIVE”
3V
Line Flyback
Input
LF
T
1 0
Monostable
Q
Logic 1 for
V
CC
< 6V
≥
1
Logic 1 for
Security at Pin 28
Inhibition
Power
Ground
2
Figure 44
TEA2028 - TEA2029APPLICATIONNOTE
22/46
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