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參數(shù)資料
| 型號(hào)： | TEA1211 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High efficiency auto-up/down DC/DC converter |
| 中文描述： | 高效率auto-up/down直流/直流轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 125K |
| 代理商： | TEA1211 |
2003 Oct 13
9
Philips Semiconductors
Preliminary specification
High efficiency auto-up/down
DC/DC converter
TEA1211HN
7.12.2
START
AND
STOP
CONDITIONS
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH
is defined as the STOP condition (P) (see Fig.7).
7.12.3
B
IT TRANSFER
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.8).
7.12.4
A
CKNOWLEDGE
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by
the transmitter during which time the receiver generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master
receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter (see Fig.9).
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered).
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that
has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to
generate a STOP condition.
handbook, full pagewidth
SDA
SCL
P
STOP condition
SDA
SCL
S
START condition
MDB007
Fig.7 START and STOP conditions on the I
2
C-bus.
handbook, full pagewidth
MDB008
data line
stable;
data valid
change
of data
allowed
SDA
SCL
Fig.8 Bit transfer on the I
2
C-bus.
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