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參數(shù)資料
| 型號： | TDA9106 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 21/30頁 |
| 文件大?。?/td> | 319K |
| 代理商： | TDA9106 |
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20k
220nF
13
From
Phase
Comparator
NOR1
A
6.5V
B
H-Lock CAP
37 HLOCKOUT
6V
5V
9
Figure 12 :
LOCK/UNLOCKBlock Diagram
OPERATINGDESCRIPTION
(continued)
When PLL1 is unlocked,the100nsnegative pulse
on A becomes much larger and consequently the
averagelevelon Pin13 decreases.It forcesHlock-
out to go high.
The Pin 13 statusis approximatelythe following:
- near 0V when there is no H-Sync
- between 0 and 4V with H-Sync frequencydiffer-
ent from VCO
- between 4 to 8 V when VCO frequencyreaches
H-Sync one (but not already in phase)
- near 8V when PLL1 is locked.
It is important to notice that Pin 13 is not an
output pin but is only used for filtering purpose
(see Figure 12).
Thelock/unlockinformationis alsoavailablethrow
I
2
C read.
II.3 - PLL2
The PLL2 ensures a constant position of the
shaped flyback signal in comparion with the saw-
tooth of the VCO (Figure 13).
H Osc
Sawtooth
H Drive
1.6V
4.0V
6.4V
7/8T
H
1/8T
H
Ts
Duty Cycle
Internally
Shaped Flyback
Flyback
9
The duty cycle of H-drive is adjustable between 30% and 60%.
Figure 13 :
PLL2 TimingDiagram
20k
Q1
GND 0V
6
HFLY
400
9
Figure 14 :
Flyback Input Electrical Diagram
The phase comparator of PLL2 (phase type com-
parator)isfollowedbya chargepumpwith
±
0.5mA
(typ.)output current.
The flybackinput is composed of an NPN transis-
tor. This input must be current driven. The maxi-
mum recommanded input current is 2mA
(see Figure 14).
The duty cycle is adjustablethrough I
2
C from30%
to 60%. For Start Up safe operation, initial duty
cycle (after Power on reset) is 60% so as to avoid
too long conductionof BU transistor.
Maximum storagetimeisabout43.75%- (Tfly/2.TH).
Typically,Tfly/THisaround20%thatmeansTsmaxis
around33.75%.
II.4 - Output Section
The H-drive signal is transmitted to the output
through a shaping block ensuring Ts and I
2
C ad-
justable duty cycle. In order to secure scanning
power part operation,the outputis inhibited in the
followingcircumstances :
- V
CC
toolow
- Xray protection activated
- During horizontalflyback
- I
2
C bitcontrol (voluntaryinhibition by MCU).
Theoutputstageis composedof a NPNDarlington
bipolartransistor.Boththecollectorandtheemittor
are accessible(see Figure16).
TheoutputDarlingtonisinoff-statewhenthepower
scanningtransistor is also in off-state.
TDA9106
21/30
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