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參數(shù)資料
| 型號(hào)： | TDA9106 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁(yè)數(shù)： | 19/30頁(yè) |
| 文件大?。?/td> | 319K |
| 代理商： | TDA9106 |
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II - HORIZONTAL PART
II.1 - Internal Input Conditions
Horizontalpart isinternallyfed by synchroproces-
sorwithadigitalsignal.correspondingtohorizontal
synchropulses or to TTLcompositeinput.
Concerning the duty cycle of the input signal, the
following signals (positive or negative) may be
appliedto the circuit.
Using internal integration, both signals are recog-
nizedonconditionthatZ/T<25%.Synchronization
occurs on the leading edge of the internal sync
signal.The minimum value of Z is 0.7
μ
s.
OPERATINGDESCRIPTION
(continued)
9
Figure 6
Another integrationis able to extractverticalpulse
ofcompositesynchroifdutycycleismorethan25%
(typicallyd = 35%).
d
d
C
TRAMEXT
9
Figure 7
Thelastfeatureperformedis the equalizingpulses
removingto avoid parasiticpulses on phasecom-
paratorinputwhichisintolerenttowrongor missing
pulse.
II.2 - PLL1
The PLL1 is composedof a phasecomparator,an
external filter and a voltage controlled oscillator
(VCO).
Thephasecomparatoris a“phasefrequency”type
designedin CMOS technology.This kindof phase
detector avoids locking on false frequencies. It is
followed by a “charge pump”, composed of two
current sources sunk and sourced (I = 1mA Typ.
when locked, I = 140
μ
A when unlocked). This
difference between lock/unlock permits a smooth
catching of horizontal frequency by PLL1. This
effectis reinforcedbyaninternaloriginalslowdown
system when PLL1 is locked avoiding Horizontal
too fast frequencychange.
The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
chargepump.A“CRC”filteris generallyused (see
Figure 8).
PLL1isinternallyinhibitedduringextractedvertical
sync (if any) to avoid taking in account missing
pulses or wrong pulses on phase comparator.The
inhibition results from the opening of a switch lo-
catedbetweenthe chargepumpand the filter(see
Figure 9). For particular synchro type, MCU can
drive Pin 3 to high level (TTL compatible input) to
inhibit PLL1. It can also be used to avoid PLL1
detectedby the MCU.
The VCO usesan externalRC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor,by a currentproportionnal
to the current in the resistor. Typical thresholdsof
sawtoothare 1.6V and 6.4V.These two levels are
accessibleto befilteredason Figure10 toimprove
jitter.
The control voltage of the VCO is typically com-
prisedbetween1.33Vand6V (seeFigure 10).The
theoricalfrequencyrangeof thisVCOis intheratio
1 to 4.5, the effective frequency range has to be
smaller 1 to 4.2 due to clamp interventionon filter
lowest value. To avoid spread of external compo-
nents and the circuit itself, it is possible to adjust
free running frequency through I
2
C. This adjust-
ment can be made automaticallyon the manufac-
turing line without manual operation by using
Hlock/unlockinformation.The adjustmentrangeis
0.8 to 1.3 F0 (where 1.3 F0 is the free running
frequencyat power on reset).
The synchro frequency has to be always higher
thanthe freerunningfrequency.As anexamplefor
a synchro range from 24kHz to 100kHz, the sug-
gested free runningfrequencyis 23kHz.
12
PLL1F
9
Figure 8
TDA9106
19/30
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