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參數(shù)資料
| 型號(hào)： | TDA9106 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽(tīng)音箱偏轉(zhuǎn)處理器 |
| 文件頁(yè)數(shù)： | 20/30頁(yè) |
| 文件大?。?/td> | 319K |
| 代理商： | TDA9106 |
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11
12
Loop
Filter
R0
1.6V
6.4V
10
C0
6.4V
1.6V
0 0.875T T
RS
FLIP FLOP
(1.3V < V
< 6V)
12
I
0
2
4 I
0
I
0
(0.80< a < 1.30)
a
I
2
C FreeRunning
Adjustment
9
8
47nF
47nF
9
Figure 10 :
Detailsof VCO
LOCKDET
13
H-LOCKCAP
COMP1
SYNC
PROCESSOR
38
H/HVIN
High
CHARGE
PUMP
Low
PLL
INHIBITION
VCO
3
PLL1INHIB
12
11
10
PLL1F
R0
C0
PHASE
ADJUST
E2
14
H-POS
I
2
C
HPOS
Adj.
OSC
TRAMEXT
TRAMEXT SMFE *
LOCK/UNLOCK
STATUS
33
VSYNCIN
1
S/G
* SMFE : Safety FrequencyMode Enable
9
Figure 9 :
PLL1 Block Diagram
OPERATINGDESCRIPTION
(continued)
An other feature is the capability for MCU to force
horizontal frequency through I
2
C to 2xF0 or 3xF0
(for burn in mode or safety requirement).In this
case,inhibitionswitch is openedleavingPLL1free
butvoltageonPLL1filterisforcedto 2.66Vfor2xF0
or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage
I
2
C adjustable between 2.8V and 4.0V (corre-
sponding to
±
10%) (see Figure 11). This voltage
has to be filteredon Pin14 so as to optimizejitter.
The TDA9106 also includes a Lock/Unlock identi-
fication block which senses in real time wheither
PLL1 is locked on the incoming horizontal sync
signalor not. Theresulting information is available
on Hlockout (see Synchro Processor). The block
functionis describedin Figure 12.
TheNOR1 gate isreceiving the phasecomparator
outputpulses (which also drive the chargepump).
When PLL1 is locked, on point A there is a very
small negative pulse (about 100ns) at each hori-
zontalcycle, so after RC filter,there is a high level
on Pin 13 whichforces Hlockout to low level.Hys-
terisis comparator detects locking when Pin 13 is
reaching 6.5V and unlocking when Pin 13 is de-
creasing to 6.0V.
H Osc
Sawtooth
Phase REF1
H Synchro
1.6V
Vb
6.4V
2.8V<Vb<4.0V
7/8T
H
1/8T
H
PhaseREF1 is obtainedby comparisonbetween thesawtoothand
a DC voltage adjustable between 2.8V and 4.0V. The PLL1 en-
sures theexact coincidence between the signals phase REFand
HSYNS. A
±
T/10phase adjustment is possible.
9
Figure 11:
PLL1Timing Diagram
TDA9106
20/30
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| TDA9109N | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:LOW-COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
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