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參數(shù)資料
| 型號： | TDA9106 |
| 廠商： | 意法半導體 |
| 英文描述： | LOW COST DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 低成本多頻監(jiān)聽音箱偏轉(zhuǎn)處理器 |
| 文件頁數(shù)： | 17/30頁 |
| 文件大?。?/td> | 319K |
| 代理商： | TDA9106 |
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OPERATINGDESCRIPTION
I - GENERALCONSIDERATIONS
I.1 - Power Supply
The typical values of the power supply voltages
V
CC
and V
DD
arerespectively12V and 5V.Perfect
operationisobtainedif V
CC
andV
DD
aremaintened
in the limits : 10.8to 13.2V and 4.5 to5.5V.
In order to avoid erratic operation of the circuit
during transient phase of V
CC
switching on, or
switchingoff,thevalueof V
CC
is monitoredand the
outputsof thecircuit areinhibitedif V
CC
islessthan
7.5V typically.
In the same manner,V
DD
is monitored and internal
set-up is made until V
DD
reaches 4V (see I
2
C
Control Tablefor power on reset).
Inordertohaveaverygoodpowersupplyrejection,
the circuit is internallypowered by several internal
voltage references (the unique typical value of
which is 8V). Two of these voltage references are
externally accessible,one for the verticalpart and
oneforthehorizontalone.Ifneeded,thesevoltage
references can be used (until load is less than
5mA).Furthermoreit is necessaryto filter the a.m.
voltagereferencesbytheuseof externalcapacitor
connectedto ground,in ordertominimizethenoise
and consequently the “jitter” on vertical and hori-
zontaloutput signals.
I.2 - I
2
C Control
TDA9106belongsto theI
2
Ccontrolleddevicefam-
ily, instead of being controlled by DC voltages on
dedicated control pins, each adjustment can be
realizedthrough the I
2
C Interface.
The I
2
C bus is a serial bus with a clockand a data
input.Thegeneralfunctionandthebusprotocolare
specified in the Philips-bus data sheets.
The interface (Data and Clock) is TTL-level com-
patible. The internal threshold level of the input
comparatoris 2.2V(when V
DD
is 5V).Spikesof up
to 50ns are filtered by an integratorand maximum
clockspeed is limited to 400kHz.
The data line (SDA) can be used in a bidirectional
way that means in read-mode the IC clocks out a
reply information(1 byte) to the micro-processor.
The bus protocol prescribes always a full-byte
transmission.Thefirst byte afterthestartcondition
is used to transmit the IC-address(7 bits-8C) and
the read/writebit (0 write - 1 read).
I.3 - Write Mode
In write mode the second byte sent contains the
subaddress of the selected function to adjust (or
controlstoaffect)andthethirdbytethecorrespond-
ing data byte.It is possible to send more than one
data byte to the IC.If afterthe thirdbyte no stop or
start condition is detected, the circuit increments
automatically the momentary subaddress in the
subaddress counter by one (auto-increment
mode).Soit is possibletotransmitimmediatelythe
next data bytes without sending the IC addressor
subaddress.It canbe usefulso asto reinitializethe
whole controls very quickly (flash manner). This
procedurecan be finished by a stop condition.
The circuit has 16 adjustment capabilities: 3 for
Horizontalpart,4 forVerticalone,2forE/Wcorrec-
tion, 2 for original Corner correction, 2 for the
Dynamic Horizontal phase control,1 for Moire op-
tion and 2 forHorizontal DynamicFocus.
20 bits are also dedicated to several controls
(ON/OFF, Horizontal Safety Frequency, Synchro
Priority, DetectionRefresh and Xrayreset).
I.4 - Read Mode
During read mode the second byte transmits the
reply information.
The reply byte contains Horizontal and Vertical
Lock/Unlockstatus,Xrayactivatedor not,the Hori-
zontal and Vertical polarity detection. It also con-
tains Synchrodetectionstatusthat is useful for
μ
P
to assignSync priority.
A stop condition always stops all activities of the
bus decoder and switches the data and the clock
line (SDAand SCL)to highimpedance.
See I
2
C Subaddressand control tables.
I.5 - SynchroProcessor
The internal Sync Processor allows the TDA9106
to acceptany kind of input synchrosignals :
- separated Horizontal & Vertical TTL-compatible
sync signals,
- composite Horizontal &Vertical TTL-compatible
sync signals,
- sync on green or compositevideo signal.
TDA9106
17/30
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