參數(shù)資料
型號(hào)： TDA8757
廠商： NXP Semiconductors N.V.
英文描述： Triple 8-bit ADC 170 Msps
中文描述： 三路8位ADC為170 MSPS
文件頁數(shù)： 17/37頁
文件大?。?/td> 895K
代理商： TDA8757
Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Preliminary data
Rev. 07 — 28 February 2002
17 of 37
9397 750 09457
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
9.
I
2
C-bus and 3W-bus interfaces
9.1 Register definitions
The configuration of the registers is given in
Table 4
.
9.1.1
Subaddress
All the registers are defined by a subaddress of 7 bits: bit Mode refers to the mode
which is used with the I
2
C-bus interface, bits ‘Sa3’ to ‘Sa0’ give the subaddress of
each register.
Bit Mode, used only with the I
2
C-bus, allows two modes for the programming:
Mode 0
Each register is programmed independently, by giving its subaddress
and its content.
All the registers are programmed one after the other, by giving this initial
condition (XXX1 1111) as the subaddress state; thus, the registers are
changed following the predefined sequence of 16 bytes (from
subaddress 0000 to 1101).
Mode 1
The default values correspond to a VESA 1280
×
1024 at 75 Hz graphic mode.
9.1.2
Offset register
This register controls the clamp level for the RGB channels. The relationship between
the programming code and the level of the clamp code is given in
Table 5
.
Table 4:
Function
name
I
2
C-bus and 3W-bus registers
Subaddress
A7 A6 A5 A4 A3 A2 A1 A0 MSB
SUBADDR
OFFSETR
X
X
X
X
COARSER X
X
X
X
FINER
X
X
X
X
OFFSETG
X
X
X
X
COARSEG X
X
X
X
FINEG
X
X
X
X
OFFSETB
X
X
X
X
COARSEB X
X
X
X
FINEB
X
X
X
X
CONTROL X
X
X
X
VCO
X
X
X
X
DIVIDER
(LSB)
PHASE
X
X
X
X
DEMUX
X
X
X
X
Bit definition
Default
value
LSB
Sa0
Or0
Cr0
Fr0
Og0
Cg0
Fg0
Ob0
Cb0
Fb0
Ip0
Di9
Di1
X
Or7
Or8
X
Og7
Og8
X
Ob7
Ob8
X
Vlevel Hlevel Edge
Z2
Z1
Di8
Di7
X
Or6
Cr6
X
Og6
Cg6
X
Ob6
Cb6
X
X
Or5
Cr5
X
Og5
Cg5
Slevel Fg4
Ob5
Cb5
X
Mode
Or4
Cr4
Fr4
Og4
Cg4
Sa3
Or3
Cr3
Fr3
Og3
Cg3
Fg3
Ob3
Cb3
Fb3
Do
Vco0
Di4
Sa2
Or2
Cr2
Fr2
Og2
Cg2
Fg2
Ob2
Cb2
Fb2
Ip2
Di11
Di3
Sa1
Or1
Cr1
Fr1
Og1
Cg1
Fg1
Ob1
Cb1
Fb1
Ip1
Di10
Di2
XXX1 0000
0111 1111
0010 0000
XXX0 0000
0111 1111
0010 0000
XXX0 0000
0111 1111
0010 0000
XXX0 0000
0000 0111
1011 1011
0100 1100
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Ob4
Cb4
Fb4
Up
Vco1
Di5
Z0
Di6
X
X
X
X
1
1
1
1
0
0
0
1
Di0
Blk
Ckrs
Cken
Ckext
Ckrp
P4
Ckdp
P3
Ckdd
P2
Shift
P1
Odda Dmx
P0
0000 0000
1000 0111
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