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參數(shù)資料
| 型號： | TDA8757 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Triple 8-bit ADC 170 Msps |
| 中文描述： | 三路8位ADC為170 MSPS |
| 文件頁數(shù)： | 15/37頁 |
| 文件大小： | 895K |
| 代理商： | TDA8757 |
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Philips Semiconductors
TDA8757
Triple 8-bit ADC 170 Msps
Preliminary data
Rev. 07 — 28 February 2002
15 of 37
9397 750 09457
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
The reference clock (CKREF) range is between 15 and 150 kHz. Consequently, the
VCO minimum frequency is 12 MHz and the maximum frequency is 170 MHz. The
gain of the VCO part can be controlled through the serial interface, depending on the
frequency range to which the PLL is locked.
Moreover, the PLL may be locked either on the rising or on the falling edge of the
CKREF signal pulses. This choice is made through the serial interface by setting
bit ‘Edge’ in register CONTROL (rising edge when bit ‘Edge’ = 0).
The charge pump current (I
cp
) enables an increase of PLL bandwidth. It is
programmable through the serial interface by setting bits ‘Ip2’, ‘Ip1’ and ‘Ip0’ in the
control register (see
Table 8
).
Different resistance values (R) for the filter can also be programmed through the
serial interface by setting the bits ‘Z2’, ‘Z1’ and ‘Z0’ in register VCO (see
Table 9
).
To have optimal PLL performance, R and I
cp
must be chosen so that:
The result of the product ‘R
×
I
cp
’ is smaller than a determined limit (Lim)
The result of the product ‘R
×
I
cp
’ is as close as possible to this limit (Lim).
(1)
where:
DR
PLL
= the divider ratio, which is the ratio between the pixel frequency and the
horizontal line frequency of the incoming signal. The setting of this parameter is
performed through the serial interface with bits Di0 to Di11. These bits are present
in the VCO-, divider- and phase registers.
f
ref
= the frequency of the signal.
K
0
= the VCO gain, which depends on the pixel frequency ranges given in
Table 10
.
In the event that several combinations of R and I
cp
give the same result, a calculation
of the damping factor (
ξ)
for each combination becomes necessary.
The combination of R and I
cp
whose damping factor is the closest to 1.5, generates
the optimal PLL performance.
(2)
where C
Z
and C
P
are the external capacitors of the PLL loop filter. The recommended
values are: C
Z
= 68 nF and C
P
= 150 pF.
The COAST signal is used to disconnect the PLL phase frequency detector during
the frame flyback (vertical blanking) or during the unavailability of the CKREF signal.
This signal can normally be derived from the VSYNC signal.
COAST may be set either active HIGH or active LOW by setting bit ‘Vlevel’ in the
control register through the serial interface (Vlevel = 0 when HIGH).
Lim
0.3
π
--------------------------------------------------
DR
K
0
=
ξ
R C
Z
2
--------------
K
I
(
DR
PLL
C
Z
C
P
+
)
----------------------------------------------
=
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