參數(shù)資料
型號: TDA8030HL
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: USB smart card reader (OTP or ROM)
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 36/57頁
文件大?。?/td> 228K
代理商: TDA8030HL
2003 Jul 04
36
Philips Semiconductors
Product specification
USB smart card reader (OTP or ROM)
TDA8030; TDA8031
8.5.2
P
HASE
-
LOCKED LOOP
A 12 to 48 MHz clock multiplier PLL is integrated on-chip. No external components are needed for the operation of the
PLL.
8.5.3
B
IT CLOCK RECOVERY
The bit clock recovery circuit recovers the clock from the incoming USB data stream using 4
×
oversampling principle.
It is able to track jitter and frequency drift as specified by the USB specification.
8.5.4
I
NTERFACE SIGNALS WITH THE MICROCONTROLLER
Table 30
The following I/O ports of the 83C51 are used for controlling the USB bus:
8.5.5
B
LOCK DIAGRAM
The digital interface consists of 3 major blocks:
The Philips Serial Interface Engine (SIE) handles the USB protocol (i.e. synchronization pattern, recognition,
parallel/serial conversion, bit stuffing/de-stuffing, CRC checking/generating, PID verification/generation, address
recognition and handshake evaluation/generation)
A Memory Management Unit (MMU), controlling the buffering of data to and from the bus
An interface to the embedded 83C51 microcontroller.
PORT
FUNCTION
DESCRIPTION
P10
USB_INT_MASK
should be set to logic 1 before entering power-down mode during suspend
and reset to logic 0 when leaving power-down mode
when set to logic 1, the internal 1.5 k
resistor is connected to pin D+
the device is ready to accept a new transaction
when LOW, this signal indicates that the bus is no longer suspended
a LOW-level will reset the USB interface
when set to logic 1, V
DDD
is applied on the optional external 1.5 k
resistor
which has been placed between pins D+ and DELATT
interrupt to the microcontroller
the device is in suspended state (TDA8030 only)
remote wake-up (TDA8030 only)
if set to logic 1, the data to the bus is a command; if set to logic 0 it is data
if set to logic 1, the USB interface is selected
P11
P12
P13
P14
P15
USB_SOFTCONNECT_INT
USB_MC_READY
USB_CLK_EN_N
USB_RESET_N
USB_SOFTCONNECT_EXT
P33
P34
P35
P25
P26
USB_INT_N
USB_SUSPEND
USB_WAKEUP_N
USB_MP_C
USB_MP_SEL
handbook, full pagewidth
MGU891
ANALOG
TRANSCEIVER
SERIAL
INTERFACE
ENGINE
OSCILLATOR
RAM
MEMORY
MANAGEMENT
UNIT
MICRO-
CONTROLLER
INTERFACE
MICRO-
CONTROLLER
D
+
D
USB bus
Fig.11 USB block diagram.
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