參數(shù)資料
型號： TDA8007B
廠商： NXP Semiconductors N.V.
英文描述： IC LOGIC 1G02 SINGLE 2-INPUT POSITIVE-NOR GATE -40+85C SOT-23-5 3000/REEL
中文描述： 雙IC卡接口的多協(xié)議
文件頁數(shù)： 21/36頁
文件大?。?/td> 159K
代理商： TDA8007B
2000 Nov 09
21
Philips Semiconductors
Product specification
Double multiprotocol IC card interface
TDA8007B
Step-up converter
Except for the V
CC
generator and the other cards contacts
buffers, the whole circuit is powered by V
DD
, and V
DDA
.
If the supply voltage is 2.5 V, then a higher voltage is
needed for the ISO contacts supply. When a card session
is requested by the microcontroller, the sequencer first
enablesthestep-upconverter(aswitchedcapacitorstype)
which is clocked by an internal oscillator at a frequency of
approximately 2.5 MHz.
Suppose that V
CC
is the maximum of V
CC1
and V
CC2
, then
there are four possible situations:
1.
V
DD
= 3 V and V
CC
= 3 V: in this case the step-up
converter acts as a doubler with a regulation of
approximately 4.0 V.
2.
V
DD
= 3 V and V
CC
= 5 V: in this case the step-up
converter acts as a tripler with a regulation of
approximately 5.5 V.
3.
V
DD
= 5 V and V
CC
= 3 V: in this case the step-up
converter acts as a follower: V
DD
is applied to V
UP
.
4.
V
DD
= 5 V and V
CC
= 5 V: in this case the step-up
converter acts as a doubler with a regulation of
approximately 5.5 V.
The recognition of the supply voltage is done by the
TDA8007B at approximately 3.5 V.
The output voltage V
UP
is fed to the V
CC
generators. V
CC
and GND are used as a reference for all other card
contacts.
ISO 7816 security
Thecorrectsequenceduringactivationanddeactivationof
the cards is ensured by two specific sequencers, clocked
by a division ratio of the internal oscillator.
Activation (START bit HIGH in PCR1 or PCR2) is only
possible if the card is present (PRES active HIGH with an
internal current source to GND) and if the supply voltage is
correct (supervisor not active).
The presence of the cards is signalled to the
microcontroller by the Hardware Status Register (HSR).
Bits PR1 or PR2 (in the USR) are set if card 1 or card 2 is
present. PRL1 or PRL2 are set if PR1 or PR2 has toggled.
During a session, the sequencer performs an automatic
emergency deactivation on one card in the event of card
take-off, or short-circuit. Both cards are automatically
deactivated in the event of a supply voltage drop, or
overheating. The hardware status register is updated and
the INT line falls, so that the system microcontroller is
aware of what happened.
Activation sequence
When the cards are inactive, V
CC
, CLK, RST, C4, C8
and I/O are LOW, with low-impedance with respect to
GND. The step-up converter is stopped.
When everything is satisfactory (voltage supply, card
present and no hardware problems), the system
microcontroller may initiate an activation sequence on a
present card.
After selecting the card and leaving the UART reset mode,
and then configuring the necessary parameters for the
counters and the UART, the START bit can be set within
the PCR (t
0
) (see Fig.8):
The step-up converter is started (t
1
); if one card was
already active, then the step-up converter was already
on and nothing more occurs at this step
V
CC
starts rising (t
2
) from 0 to 5 V or 3 V with a
controlled rise time of 0.17 V/
μ
s (typ.)
I/O rises to V
CC
(t
3
); C4 and C8 also rise if bits
C4 and C8 within the PCR have been set to logic 1
(integrated 10 k
pull-up resistors to V
CC
)
The CLK is sent to the card and RST is enabled (t
4
).
After a number of CLK pulses that can be counted with the
time-out counter, bit RSTIN may be set by software: RST
will then rise to V
CC
.
The sequencer is clocked by
1
64
f
int
which leads to a time
interval of t = 25
μ
s (typ.). Thus t
1
= 0 to
1
64
t, t
2
= t
1
+
3
2
t,
t
3
= t
1
+
7
2
t and t
4
= t
1
+ 4t.
Deactivation sequence
When the session is completed, the microcontroller resets
START HIGH (t
10
). The circuit then executes an automatic
deactivation sequence (see Fig.9):
The card is reset (RST falls LOW) (t
11
)
The CLK is stopped (t
12
)
I/O, C4 and C8 fall to 0 V (t
13
)
V
CC
falls to 0 V with typical 0.17 V/
μ
s slew rate (t
14
)
The step-up converter is stopped and CLK, RST, V
CC
and I/O become low-impedance to GND (t
15
) (if both
cards are inactive).
t
11
= t
10
+
1
64
t, t
12
= t
11
+
1
2
t, t
13
= t
11
+ t, t
14
= t
11
+
3
2
t
and t
15
= t
11
+
7
2
t.
t
de
= time that V
CC
needs to decrease to less than 0.4 V.
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