2000 Nov 09
12
Philips Semiconductors
Product specification
Double multiprotocol IC card interface
TDA8007B
Table 5
Time-out register 3 (write only); address: B (all bits are cleared after reset)
Table 6
Time-out configuration register (read and write); address: 8 (all bits are cleared after reset)
Table 7
Time-out counter configurations
TO37
TO36
TO35
TO34
TO33
TO32
TO31
TO30
TOL23
TOL22
TOL21
TOL20
TOL19
TOL18
TOL17
TOL16
TOC7
TOC6
TOC5
TOC4
TOC3
TOC2
TOC1
TOC0
TOC7
TOC6
TOC5
TOC4
TOC3
TOC2
TOC1
TOC0
TOC
OPERATING MODE
00
61
all counters are stopped
Counter 1 is stopped, and counters 3 and 2 form a 16-bit counter. Counting the value stored in TOR3
and TOR2 is started after 61 is written in the TOC. An interrupt is given, and bit TO3 is set within the
USR when the terminal count is reached. The counter is stopped by writing 00 in the TOC.
Counter 1 is an 8-bit auto reload counter, and counters 3 and 2 form a 16-bit counter. Counter 1 starts
counting the content of TOR1 on the first start bit (reception or transmission) detected on I/O after 65 is
written in the TOC. When counter 1 reaches its terminal count, an interrupt is given, bit TO1 in the USR
is set, and the counter automatically restarts the same count until it is stopped. It is not allowed to
change the content of TOR1 during a count. In this mode, the accuracy of counter 1 is
±
0.5 ETU.
Counters 3 and 2 are wired as a single 16-bit counter and starts counting the value TOR3 and TOR2
when 65 is written in the TOC. When the counter reaches its terminal count, an interrupt is given and
bit TO3 is set within the USR. Both counters are stopped when 00 is written in the TOC.
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and
TOR1 is started after 68 is written in the TOC. The counter is stopped by writing 00 in the TOC. It is not
allowed to change the content of TOR3, TOR2 and TOR1 within a count.
Counters 3, 2 and 1 are wired as a single 24-bit counter. Counting the value stored in TOR3, TOR2 and
TOR1 on the first start bit detected on I/O (reception or transmission) after the value has been written.
It is possible to change the content of TOR3, TOR2 and TOR1 during a count; the current count will not
be affected and the new count value will be taken into account at the next start bit. The counter is
stopped by writing 00 in the TOC. In this configuration TOR3, TOR2 and TOR1 must not be all zero.
Same configuration as TOC = 65, except that counter 1 will be stopped at the end of the 12th ETU
following the first start bit detected after E5 has been written in the TOC.
65
68
7C
E5