參數(shù)資料
型號(hào)： TDA8007B
廠商： NXP Semiconductors N.V.
英文描述： IC LOGIC 1G02 SINGLE 2-INPUT POSITIVE-NOR GATE -40+85C SOT-23-5 3000/REEL
中文描述： 雙IC卡接口的多協(xié)議
文件頁(yè)數(shù)： 18/36頁(yè)
文件大?。?/td> 159K
代理商： TDA8007B
2000 Nov 09
18
Philips Semiconductors
Product specification
Double multiprotocol IC card interface
TDA8007B
Clock Configuration Register (see Table 19):
For cards 1 and 2, the CCR defines the clock for the
selected card.
For cards 1, 2 and 3 it defines the clock to the
ISO UART. It should be noted that if bit CKU in the
prescaler register of the selected card is set, then the
ISO UART is clocked at twice the frequency of the card,
which allows baud rates not foreseen in ISO 7816 norm
to be reached.
In case of an asynchronous card, the Clock Stop (CST) bit
defines whether the clock to the card is stopped or not.
If CST is set, then CLK is stopped LOW if SHL = 0, and
HIGH if SHL = 1.
If CST is reset, then CLK is determined by bits AC0, AC1
and AC2; see Table 16. All frequency changes are
synchronous, thus ensuring that no spike or unwanted
pulse widths occur during changes.
Table 16
CLK value for an asynchronous card
When switching from XTAL/n to
1
2
f
int
or vice verse, only
bit AC2 must be changed (AC1 and AC0 must remain the
same). When switching from XTAL/n or
1
2
f
int
to CLK
STOP or vice verse, only bits CST and SHL must be
changed.
When switching from XTAL/n to
1
2
f
int
or vice verse, a
maximum delay of 200
μ
s can occur between the
command and the effective frequency change on CLK(the
fastest switching time is from
1
2
XTAL to
1
2
f
int
or vice
verse, the best for duty cycle is from
1
8
XTAL to
1
2
f
int
or
vice verse).
It is necessary to wait the maximum delay time before
reactivating from Power-down mode.
In the event of a synchronous card, then the CLK contact
isthecopyof thevaluewritten in Synchronous Clock(SC).
In reception mode, the data from the card is available to
UR0 after a read operation of the URR; in transmission
mode, the data is written on the I/O line of the card when
theUTRhasbeenwrittentoandremainsunchangedwhen
another card is selected.
The Power Control Register (PCR), see Table 20:
Starts or stops card sessions.
Reads or writes on auxiliary card contacts C4 and C8.
Is available only for cards 1 or 2.
If the microcontroller sets START to logic 1, then the
selected card is activated (see Section “Activation
sequence”). If the microcontroller resets START to logic 0,
then the card is deactivated (see Section “Deactivation
sequence”). START is automatically reset in case of
emergency deactivation.
If 3 V/5 V is set to logic 1, then V
CC
is 3 V. If 3 V/5 V is set
to logic 0, then V
CC
is 5 V.
When the card is activated, RST is the copy of the value
written in RSTIN.
If 1.8 V is set, then V
CC
= 1.8 V: It should be noted that no
specification is guaranteed at this voltage.
When writing to the PCR, C4 will output the value written
to PCR4,and C8thevaluewrittento PCR5.Whenreading
from the PCR, PCR4 will store the value on C4, and PCR5
the value on C8.
AC2
AC1
AC0
CLK
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
XTAL
1
2
XTAL
1
4
XTAL
1
8
XTAL
1
2
f
int
1
2
f
int
1
2
f
int
1
2
f
int
Table 17
Guard time register (GTR1, 2 and 3) (read and write); address: 5 (all bits are cleared after reset)
Table 18
UART configuration register 1 (UCR11, 12 and 13) (read and write); address: 6
(all relevant bits are cleared after reset)
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
GT7
GT6
GT5
GT4
GT3
GT2
GT1
GT0
UC7
UC6
UC5
UC4
UC3
UC2
UC1
UC0
not used
FIP
FC
PROT
T/R
LCT
SS
CONV
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