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參數(shù)資料
| 型號： | TDA7546TR |
| 廠商： | 意法半導體 |
| 英文描述： | Multichip module for TMC tuner applications |
| 中文描述： | 豐田汽車多芯片模塊調(diào)諧器應(yīng)用 |
| 文件頁數(shù)： | 51/68頁 |
| 文件大?。?/td> | 823K |
| 代理商： | TDA7546TR |
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TDA7546
Software specifications
51/68
Table 37.
rds_int register
Table 38.
rds_qu register
(1) If the interrupt source is changed form block A, B,
D, TA, TA EON to another one "no interrupt" must be
set before to clear the previous interrupt acknowledge.
Interrupt bit. It is set to one on every programmed interrupt. It is
reset by reading rds_int register. The inverted version is also
externally available on RDSINT pin.
itsrc[2:0] selects interrupt source (1).
Block A, B, D and TA, TA EON interrupts only if "synch" =1.
Synchronization information (refer to pages 28-29).
1: The module is already synchronized.
0: The module is synchronizing.
It is used to force a resynchronization. If it is set to one, the RDS
modules are forced to resynchronization state and the RAM buffer
address is reset.
This bit is reset automatically. It is read always as zero.
Buffer not empty.
1: At least one block is present in the RAM buffer.
0: The RAM buffer is empty.
rds_int, rds_bd_ctrl and pllreg4-0 write order.
This bit is only used in SPI mode and is read always as zero
.
1: Update of rds_int, rds_bd_ctrl and pllreg4-0 with data shifted in.
0: No update of rds_int, rds_bd_ctrl and pllreg4-0.
bit name
access
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
r
r/w
r
r/w
r
r/w
r/w
r/w
itsrc0
int
ar_res
bne
itsrc1
synch
write
reset value
0
0
0
0
0
0
0
0
itsrc2
(1)
itsrc2
0
0
1
1
0
0
0
0
itsrc1
interrupt source
itsrc0
buffer not empty
buffer full
block B
block D
TA
TA EON
block A
no interrupt
0
0
0
1
1
1
1
1
1
0
1
0
1
1
0
1
rds_int
(2) If "syncw"=1 of rds_bd_ctrl register, the block counter in-
dicates the expected RDS block.
(3) qu[3...0] counts the number of bits (max.16) which are
marked as bad by the demodulator within each RDS block.
It could be used as a quality information, indicating the max-
imum number of bits which are allowed to be corrected.
It indicates if error correction was successful.
1: The syndrome was zero after error correction.
0: The syndrome did not become zero and therefore the error
correction was not successful.
1: Block E is detected. This indicates a paging block which is
deTned in the RBDS speciTcation used in the United States of
America.
0: An ordinary RDS block A, B, C, C or D is detected, or no valid
syndrome was found.
Bit 0 of block counter (2).
bit 1 of block counter (2).
bit 0 of quality counter
(3).
bit 1 of quality counter
(3).
bit 2 of quality counter (3).
bit 3 of quality counter (3).
bit name
access
bit 7
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
r
r
r
r
r
r
r
synz
e
qu0
qu3
qu1
qu2
blk1
blk0
blk1
1
0
0
0
blk0
block A
block name
block D
1
block C,C'
0
block B
1
1
(2)
reset value
0
0
0
0
0
0
0
0
rds_qu
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