參數(shù)資料
型號(hào)： TCS59SM816BFTL-80
廠商： Toshiba Corporation
英文描述： 4M×4Banks×16Bits Synchronous DRAM(4組4M×16位同步動(dòng)態(tài)RAM)
中文描述： 4米× 4Banks × 16位同步DRAM（4組4米× 16位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 30/49頁(yè)
文件大?。?/td> 2423K
代理商： TCS59SM816BFTL-80
TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 30/49
CHIP SELECT:
The CS input controls the latching of the commands on the positive edges of CLK when CS is asserted
“l(fā)ow”. No commands are latched as long as CS is held “high”.
ROW ADDRESS STROBE:
The RAS input defines the operation commands in conjunction with the CAS and WE inputs, and is
latched at the positive edges of CLK. When RAS and CS are asserted “l(fā)ow” and CAS is asserted “high”,
either the Bank Activate command or the Precharge command is selected by the WE signal. When WE is
asserted “high”, the Bank Activate command is selected and the bank designated by BS0, BS1 are turned on so
that it is in the active state. When WE is asserted “l(fā)ow”, the Precharge command is selected and the bank
designated by BS0, BS1 are switched to the idle state after Precharge operation.
COLUMN ADDRESS STROBE:
The CAS input defines the operation commands in conjunction with the RAS and WE inputs, and is
latched at the positive edges of CLK. When RAS is held “high” and CS is asserted “l(fā)ow”, column access is
started by asserting CAS “l(fā)ow”. Then, the Read or Write command is selected by asserting WE “l(fā)ow” or
“high”.
WRITE ENABLE:WE
The WE input defines the operation commands in conjunction with the RAS and CAS inputs, and is
latched at the positive edges of CLK. The WE input is used to select the Bank Activate or Precharge command
and Read or Write command.
DATA INPUT/OUTPUT MASK: DQM or LDQM and UDQM
The DQM input enables output in a Read cycle and functions as the input data mask in a Write cycle. When
DQM is asserted “high” at the positive edges of CLK, output data is disabled after two clock cycles during a
Read cycle, and input data is masked at the same clock cycle during a Write cycle.
In the case of the TC59SM816BFT/BFTL, the LDQM and UDQM inputs function as byte data control. The
LDQM input can control DQ0~DQ7 in a Read or Write cycle and the UDQM can control DQ8~DQ15 in a Read
or Write cycle.
DATA INPUT/OUTPUT: DQ0~DQ15
The DQ0~DQ15 input and output data are synchronized with the positive edges of CLK. In the case of
TC59SM808BFT/BFTL and TC59SM804BFT/BFTL, these pins are DQ0~DQ7 and DQ0~DQ3 respectively.
CS
RAS
CAS
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