參數(shù)資料
型號(hào)： TCS59SM804BFTL-75
廠商： Toshiba Corporation
英文描述： 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動(dòng)態(tài)RAM)
中文描述： 1,600 × 4Banks × 4Bits同步DRAM（4組1,600 × 4位同步動(dòng)態(tài)RAM）的
文件頁(yè)數(shù)： 36/49頁(yè)
文件大?。?/td> 2423K
代理商： TCS59SM804BFTL-75
TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 36/49
4. Precharge
There are two commands which perform the Precharge operation: Bank Precharge and Precharge All. When
the Bank Precharge command is issued to the active bank, the bank is precharged and then switched to the idle
state. The Bank Precharge command can precharge one bank independently of the other bank and hold the
unprecharged bank in the active state. The maximum time each bank can be held in the active state is specified
as t
RAS
(max). Therefore, each bank must be precharged within t
RAS
(max) from the Bank Activate command.
The Precharge All command can be used to precharge all banks simultaneously. Even if banks are not in the
active state, the Precharge All command can still be issued. In this case, the Precharge operation is performed
only for the active bank and the precharged bank is then switched to the idle state.
5. Page Mode
The Read or Write command can be issued on any clock cycle.
Whenever a Read operation is to be interrupted by a Write command, the output data must be masked by
DQM to avoid I/O conflict. Also, when a Write operation is to be interrupted by a Read command, only the input
data before the Read command is enable and the input data after the Read command is disabled.
6. Burst Termination
When the Precharge command is issued for a bank in a Burst cycle, the Burst operation is terminated. When
the Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of
(CAS latency-1) from the Precharge command (Figure 20). When the Burst Write cycle is interrupted by the
Precharge command, the input circuit is reset at the same clock cycle at which the Precharge command is issued.
In this case, the DQM signal must be asserted “High” to prevent writing the invalid data to the cell array
(Figure 20).
When the Burst Stop command is issued for the bank in a Full-page Burst cycle, the Burst operation is
terminated. When the Burst Stop command is issued during Full-page Burst Read cycle, read operation is
disabled after clock cycle of (CAS latency-1) from the Burst Stop command. When the Burst Stop command is
issued during a Full-page Burst Write cycle, write operation is disabled at the same clock cycle at which the
Burst Stop command is issued. (Figure 19)
相關(guān)PDF資料
PDF描述
TCS59SM804BFTL-80 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動(dòng)態(tài)RAM)
TCS59SM808BFT-75 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動(dòng)態(tài)RAM)
TCS59SM808BFT-80 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動(dòng)態(tài)RAM)
TCS59SM808BFTL-70 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動(dòng)態(tài)RAM)
TCS59SM808BFTL-75 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動(dòng)態(tài)RAM)
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