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參數(shù)資料
| 型號： | TCS59SM804BFTL-75 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| 中文描述： | 1,600 × 4Banks × 4Bits同步DRAM（4組1,600 × 4位同步動態(tài)RAM）的 |
| 文件頁數(shù)： | 35/49頁 |
| 文件大?。?/td> | 2423K |
| 代理商： | TCS59SM804BFTL-75 |
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TC59SM816/08/04BFT/BFTL-70,-75,-80
2000-03-14 35/49
2. Read Operation
Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is
issued after t
RCD
from the Bank Activate command, the data is read out sequentially, synchronized to the
positive edges of CLK (a Burst Read operation). The initial read data becomes available after CAS Latency
from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. In
addition, the burst length of read data and Addressing Mode must be set. Each bank is held in the active state
unless the Precharge command is issued, so that the sense amplifiers can be used as secondary cache.
When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any
other commands. Also, when the Burst Length is 1 and t
RCD
(min), the timing from the RAS command to the
start of the Auto Precharge operation is shorter than t
RAS
(min). In this case, t
RAS
(min) must be satisfied by
extending t
RCD
(Figure 9, 15).
When the Precharge operation is performed on a bank during a Burst Read operation, the Burst operation is
terminated (Figure 20).
When the Burst Length is full-page, column data is repeatedly read out until the Burst Stop command or
Precharge command is issued.
3. Write Operation
Issuing the Write command after t
RCD
from the Bank Activate command, the input data is latched
sequentially, synchronizing with the positive edges of CLK after the Write command (Burst Write operation).
The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at
power-up.
When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically
after the Write cycle, then the bank is switched to the idle state. This command cannot be interrupted by any
other command for the entire burst data duration. Also, when the Burst Length is 1 and t
RCD
(min), the timing
from the RAS command to the start of the Auto Precharge operation is shorter than t
RAS
(min). In this case,
t
RAS
(min) must be satisfied by extending t
RCD
(Figure 10, 16).
When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is
terminated (Figure 20).
When the Burst Length is full-page, the input data is repeatedly latched until the Burst Stop command or the
Precharge command is issued.
When the Burst Read and Single Write mode is selected, the write burst length is 1 regardless of the read
burst length.
相關(guān)PDF資料 |
PDF描述 |
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| TCS59SM804BFTL-80 | 16M×4Banks×4Bits Synchronous DRAM(4組16M×4位同步動態(tài)RAM) |
| TCS59SM808BFT-75 | 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動態(tài)RAM) |
| TCS59SM808BFT-80 | 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動態(tài)RAM) |
| TCS59SM808BFTL-70 | 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動態(tài)RAM) |
| TCS59SM808BFTL-75 | 8M×4Banks×8Bits Synchronous DRAM(4組8M×8位同步動態(tài)RAM) |
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