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參數資料
| 型號： | TC1130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32-Bit Single-Chip Microcontroller |
| 中文描述： | 32位單片機 |
| 文件頁數： | 60/113頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | TC1130 |
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TC1130
Data Sheet
56
V0.3, 2003-09
System Timer
The STM within the TC1130 is designed for global system timing applications requiring
both high precision and long range. The STM provides the following features:
Free-running 56-bit counter
All 56 bits can be read synchronously
Different 32-bit portions of the 56-bit counter can be read synchronously
Flexible interrupt generation on partial STM content compare match
Driven by clock
f
STM
after reset (default after reset is
f
STM
=
f
SYS
= 150 MHz)
Counting starts automatically after a reset operation
STM is reset under following reset causes:
– Wake-up reset (PMG_CON.DSRW must be set)
– Software reset (RST_REQ.RRSTM must be set)
– Power-on reset
STM (and clock divider) is not reset at watchdog reset and hardware reset (HDRST =
0)
The STM is an upward counter, running with the system clock frequency
f
SYS
(after reset
f
STM
=
f
SYS
). It is enabled per default after reset, and immediately starts counting up.
Other than via reset, it is no possible to affect the contents of the timer during normal
operation of the application, it can only be read, but not written to. Depending on the
implementation of the clock control of the STM, the timer can optionally be disabled or
suspended for power-saving and debugging purposes via a clock control register
The maximum clock period is 2
56
/
f
STM
. At
f
STM
= 150 MHz (maximum), for example, the
STM counts 15.2 years before overflowing. Thus, it is capable of continuously timing the
entire expected product life-time of a system without overflowing.
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