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參數(shù)資料
| 型號(hào)： | TC1130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32-Bit Single-Chip Microcontroller |
| 中文描述： | 32位單片機(jī) |
| 文件頁(yè)數(shù)： | 40/113頁(yè) |
| 文件大?。?/td> | 1505K |
| 代理商： | TC1130 |
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TC1130
Data Sheet
36
V0.3, 2003-09
MultiCAN
Figure 12
shows a global view of all functional blocks of the MultiCAN module.
Figure 12
General Block Diagram of the MultiCAN Interfaces
The MultiCAN module contains 4 Full-CAN nodes operating independently or
exchanging data and remote frames via a gateway function. Transmission and reception
of CAN frames is handled in accordance to CAN specification V2.0 part B (active). Each
CAN node can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers.
All CAN nodes share a common set of message objects, where each message object
may be individually allocated to one of the CAN nodes. Besides serving as a storage
container for incoming and outgoing frames, message objects may be combined to build
gateways between the CAN nodes or to setup a FIFO buffer.
The message objects are organized in double chained lists, where each CAN node has
it’s own list of message objects. A CAN node stores frames only into message objects
that are allocated to the list of the CAN node. It only transmits messages from objects of
this list.
A powerful, command driven list controller performs all list operations.
MultiCAN Module Kernel
MultiCAN_TC1130_impl
Interrupt
Control
f
CAN
f
CLC
Port 0
Control
CAN
Node 1
CAN Control
Message
Object
Buffer
128
Objects
TXDC0A
RXDC0A
CAN
Node 0
CAN
Node 2
CAN
Node 3
TXDC1A
RXDC1A
TXDC1B
TXDC2
RXDC2
TXDC3
RXDC3
Linked
List
Control
P0.15 /
TXDCAN3
P0.14 /
RXDCAN3
P0.13 /
TXDCAN2
P0.12 /
RXDCAN2
P0.11 /
TXDCAN1A
P0.10 /
RXDCAN1A
P0.9 /
TXDCAN0A
P0.8 /
RXDCAN0A
P1.1 /
TXDCAN0B
P1.0 /
RXDCAN0B
Clock
Control
Address
Decoder
DMA
INT_O
[3:0]
INT_O
[15:4]
INT_O15
Port 1
Control
P1.3 /
TXDCAN1B
P1.2 /
RXDCAN1B
RXDC1B
TXDC0B
RXDC0B
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