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參數(shù)資料
| 型號： | TC1130 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 32-Bit Single-Chip Microcontroller |
| 中文描述： | 32位單片機(jī) |
| 文件頁數(shù)： | 30/113頁 |
| 文件大?。?/td> | 1505K |
| 代理商： | TC1130 |
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TC1130
Data Sheet
26
V0.3, 2003-09
Inter IC Serial Interface (IIC)
Figure 7
shows a global view of the functional blocks of the Inter IC Serial Interface (IIC).
The IIC module has four I/O lines, located at Port 2. The IIC module is further supplied
by a clock control, interrupt control, and address decoding logic. One DMA request can
be generated by IIC module.
Figure 7
General Block Diagram of the IIC Interface
The on-chip IIC Bus module connects the platform buses to other external controllers
and/or peripherals via the two-line serial IIC interface. One line is responsible for clock
transfer and synchronization (SCL), the other is responsible for the data transfer (SDA).
The IIC Bus module provides communication at data rates of up to 400 Kbit/s and
features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to
the IIC bus protocol.
The module can operate in three different modes:
Master mode
, where the IIC controls the bus transactions and provides the clock signal.
Slave mode
, where an external master controls the bus transactions and provides the
clock signal.
Multimaster mode
, where several masters can be connected to the bus, i.e. the IIC can
be master or slave.
The on-chip IIC bus module allows efficient communication via the common IIC bus. The
module unloads the CPU of low level tasks like
(De)Serialization of bus data.
Generation of start and stop conditions.
Monitoring the bus lines in slave mode.
Evaluation of the device address in slave mode.
Bus access arbitration in multimaster mode.
Address
Decoder
Interrupt
Control
IIC
Module
Port 2
Control
P2.13/SCL0
P2.15/SCL1
SDA0
P2.14/SDA1
P2.12/SDA0
Clock
Control
f
IIC
SCL0
SDA1
SCL1
INT_P
INT_E
INT_D
to DMA
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