參數(shù)資料
型號: TAS5518CPAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 48/103頁
文件大?。?/td> 2007K
代理商: TAS5518CPAGR
3.4
Master Clock and Serial Data Rate Controls
3.4.1
PLL Operation
3.5
Bank Controls
TAS5518C
8-Channel Digital Audio PWM Processor
www.ti.com
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
connected to the TAS5518C output needs to get ready for the next on-time period. The maximum possible
modulation is then set by the power stage requirements. The default modulation index limit setting is
97.7%; however, some power stages may require a lower modulation limit. See the applicable power
stage data sheet for details on setting the modulation index limit. The default setting of 97.7% can be
changed in the modulation index register (0x16).
The TAS5518C functions only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that control the flow of data on the four serial data interfaces. The 13.5-MHz
external crystal allows the TAS5518C to detect MCLK and the data rate automatically.
The MCLK frequency can be 64 fS, 128 fS, 196 fS, 256 fS, 384 fS, 512 fS, or 768 fS.
The TAS5518C operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, the phase relationship of these signals has no constraint. The TAS5518C accepts a 64 fS SCLK
rate and a 1 fS LRCLK.
If the phase of SCLK or LRCLK drifts more than
±10 MCLK cycles since the last reset, the TAS5518C
senses a clock error and resynchronizes the clock timing.
The clock and serial data interface have several control parameters:
MCLK ratio (64 f
S, 128 fS, 196 fS, 256 fS, 384 fS, 512 fS, or 768 fS) – I
2C parameter
Data rate (32, 38, 44.1, 48, 88.2, 96, 176.4, 192 kHz) – I2C parameter
AM mode enable/disable – I2C parameter
During AM interference avoidance, the clock control circuitry uses three other configuration inputs:
Tuned AM frequency (for AM interference avoidance) (550 kHz to 1750 kHz) – I2C parameter
Frequency set select (1–4) – I2C parameter
Sample rate – I2C parameter or auto-detected
The TAS5518C uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital
PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL
provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz
crystal provides the input reference clock for the DPLL. The crystal provides a time base to support a
number of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions.
The crystal time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5518C can receive and store I2C commands and provide status.
The TAS5518C permits the user to specify and assign sample-rate-dependent parameters for biquad,
loudness, DRC, and tone in one of three banks that can be manually selected or selected automatically
based on the data sampling rate. Each bank can be enabled for one or more specific sample rates via I2C
bank control register 0x40. Each bank set holds the following values:
Coefficients for seven biquads (7 × 5 = 35 coefficients) for each of the eight channels (registers
0x51–0x88)
Coefficients for one loudness biquad (register 0x95)
DRC1 energy and (1 – energy) values (register 0x98)
DRC1 attack, (1 – attack), decay, (1 – decay) values (register 0x9C)
DRC2 energy and (1 – energy) values (register 0x9D)
DRC2 attack, (1 – attack), decay, (1 – decay) values (register 0xA1)
TAS5518C Controls and Status
49
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