參數(shù)資料
型號: TAS5518CPAG
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 73/103頁
文件大?。?/td> 2007K
代理商: TAS5518CPAG
7
Serial-Control Interface Register Definitions
7.1
Clock Control Register (0x00)
7.2
General Status Register 0 (0x01)
7.3
Error Status Register (0x02)
TAS5518C
8-Channel Digital Audio PWM Processor
www.ti.com
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
Unless otherwise noted, the I2C register default values are in bold font.
Note that u indicates unused bits.
Bit D1 is don't care.
Table 7-1. Clock Control Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
X
32-kHz data rate
0
1
X
38-kHz data rate
0
1
0
X
44.1-kHz data rate
0
1
X
48-kHz data rate
1
0
X
88.2-kHz data rate
1
0
1
X
96-kHz data rate
1
0
X
176.4-kHz data rate
1
X
192-kHz data rate
0
X
MCLK frequency = 64
0
1
X
MCLK frequency = 128
0
1
0
X
MCLK frequency = 192
0
1
X
MCLK frequency = 256
1
0
X
MCLK frequency = 384
1
0
1
X
MCLK frequency = 512
1
0
X
MCLK frequency = 768
1
X
Reserved
X
1
Clock register is valid (read-only)
X
0
Clock register is not valid (read-only)
Table 7-2. General Status Register Format
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
Clip indicator
1
Bank switching busy
0
1
Identification code for TAS5518C
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software
must clear the register (write zeroes) and than read them to determine if there are any persistent errors.
Table 7-3. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
1
PLL phase lock error
1
PLL auto lock error
1
SCLK error
1
LRCLK error
1
Frame slip
Serial-Control Interface Register Definitions
71
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