參數(shù)資料
型號: TAS5518CPAG
廠商: TEXAS INSTRUMENTS INC
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數(shù): 27/103頁
文件大?。?/td> 2007K
代理商: TAS5518CPAG
TAS5518C
8-Channel Digital Audio PWM Processor
www.ti.com
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
3.2.2
Power Down (PDN)
............................................................................................. 44
3.2.3
Back-End Error (BKND_ERR)
................................................................................. 44
3.2.3.1
BKND_ERR and VALID
.............................................................................. 45
3.2.4
Speaker/Headphone Selector (HP_SEL)
..................................................................... 45
3.2.5
Mute (MUTE)
..................................................................................................... 45
3.3
Device Configuration Controls
............................................................................................ 46
3.3.1
Channel Configuration Registers
.............................................................................. 46
3.3.2
Headphone Configuration Registers
.......................................................................... 47
3.3.3
Audio System Configurations
.................................................................................. 47
3.3.3.1
Using Line Outputs in 6-Channel Configurations
................................................. 48
3.3.4
Recovery from Clock Error
..................................................................................... 48
3.3.5
Power-Supply Volume-Control Enable
....................................................................... 48
3.3.6
Volume and Mute Update Rate
................................................................................ 48
3.3.7
Modulation Index Limit
.......................................................................................... 48
3.4
Master Clock and Serial Data Rate Controls
........................................................................... 49
3.4.1
PLL Operation
.................................................................................................... 49
3.5
Bank Controls
............................................................................................................... 49
3.5.1
Manual Bank Selection
......................................................................................... 50
3.5.2
Automatic Bank Selection
...................................................................................... 50
3.5.2.1
Coefficient Write Operations While Automatic Bank Switch Is Enabled
....................... 50
3.5.3
Bank Set
.......................................................................................................... 50
3.5.4
Bank-Switch Timeline
........................................................................................... 51
3.5.5
Bank-Switching Example 1
..................................................................................... 51
3.5.6
Bank-Switching Example 2
..................................................................................... 51
4
Electrical Specifications
...................................................................................................... 52
4.1
Absolute Maximum Ratings
............................................................................................... 52
4.1.1
Dissipation Rating Table (High-k Board, 105
°C Junction) ................................................. 52
4.2
Dynamic Performance
......................................................................................... 52
4.3
Recommended Operating Conditions
........................................................................ 53
4.4
Electrical Characteristics
....................................................................................... 53
4.5
PWM Operation
.................................................................................................. 53
4.6
Switching Characteristics
....................................................................................... 54
4.6.1
Clock Signals
..................................................................................................... 54
4.6.2
Serial Audio Port
................................................................................................. 54
4.6.3
I
2C Serial Control Port Operation
.............................................................................. 55
4.6.4
Reset Timing (RESET)
......................................................................................... 57
4.6.5
Power-Down (PDN) Timing
.................................................................................... 57
4.6.6
Back-End Error (BKND_ERR)
................................................................................. 58
4.6.7
Mute Timing (MUTE)
............................................................................................ 58
4.6.8
Headphone Select (HP_SEL)
.................................................................................. 59
4.6.9
Volume Control
.................................................................................................. 59
4.7
Serial Audio Interface Control and Timing
................................................................... 60
4.7.1
I
2S Timing
........................................................................................................ 60
4.7.2
Left-Justified Timing
............................................................................................. 61
4.7.3
Right-Justified Timing
........................................................................................... 62
5
I2C Serial-Control Interface (Slave Addresses 0x36 and 0x37)
.................................................. 63
5.1
General I
2C Operation
..................................................................................................... 63
5.2
Single- and Multiple-Byte Transfers
..................................................................................... 64
5.3
Single-Byte Write
........................................................................................................... 64
5.4
Multiple-Byte Write
......................................................................................................... 65
5.5
Incremental Multiple-Byte Write
.......................................................................................... 65
5.6
Single-Byte Read
........................................................................................................... 66
Contents
3
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