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參數(shù)資料
| 型號： | TAS5518CPAG |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 64/103頁 |
| 文件大?。?/td> | 2007K |
| 代理商： | TAS5518CPAG |
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5
I
2C Serial-Control Interface (Slave Addresses 0x36 and 0x37)
5.1
General I
2C Operation
7-BitSlave Address
R/
W
8-BitRegister Address(N)
A
8-BitRegisterDataFor
Address(N)
Start
Stop
SDA
SCL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
A
8-BitRegisterDataFor
Address(N)
A
T0035-01
TAS5518C
8-Channel Digital Audio PWM Processor
www.ti.com
SLES238A – SEPTEMBER 2008 – REVISED JULY 2009
The TAS5518C has a bidirectional I2C interface that is compatible with the Inter-IC (I2C) bus protocol and
supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read
operations. This is a slave-only device that does not support a multimaster bus environment or wait state
insertion. The control interface is used to program the registers of the device and to read device status.
The TAS5518C supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus
operation (400 kHz maximum). The TAS5518C performs all I2C operations without I2C wait cycles.
The I2C write address is 0x36 and the I2C read address is 0x37.
The I2C bus employs two signals—SDA (data) and SCL (clock)—to communicate between integrated
circuits in a system. Data is transferred on the bus serially, one bit at a time. The address and data can be
transferred in byte (8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte
transferred on the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer
operation begins with the master device driving a start condition on the bus and ends with the master
device driving a stop condition on the bus. The bus uses transitions on SDA while the clock is high to
indicate start and stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high
transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period.
These conditions are shown in Figure 5-1. The master generates the 7-bit slave address and the
read/write (R/W) bit to open communication with another device and then waits for an acknowledge
condition. The TAS5518C holds SDA low during the acknowledge clock period to indicate an
acknowledgement. When this occurs, the master transmits the next byte of the sequence. Each device is
addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the same
signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
Figure 5-1. Typical I2C Sequence
The number of bytes that can be transmitted between start and stop conditions is unlimited. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer
sequence is shown in Figure 5-1.
The 7-bit address for the TAS5518C is 0011011. When the R/W bit is added as the LSB, the I2C write
address is 0x36 and the I2C read address is 0x37.
63
I2C Serial-Control Interface (Slave Addresses 0x36 and 0x37)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| TAS5518CPAGR | 功能描述:音頻 DSP 8Ch Dig Audio PWM Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5518PAG | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5518PAG | 制造商:Texas Instruments 功能描述:Pulse Width Modulation (PWM) Controller |
| TAS5518PAGG4 | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TAS5518PAGR | 功能描述:音頻 DSP 8 Ch Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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