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參數(shù)資料
| 型號： | T35L6464A |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 64 SRAM |
| 中文描述： | 64K的× 64的SRAM |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 160K |
| 代理商： | T35L6464A |
TE
CH
tm
GENERAL
(ADSC, ADSP ,and
ADV
), write enables (
BW1
,
BW2
,
BW3
,
BW4
,
BW5
,
BW6
,
BW7
,
BW8
and
BWE
), and global write (
GW
).
Asynchronous inputs include the output enable
(
OE
) , Snooze enable (ZZ) and burst mode control
(MODE). The data outputs (Q), enabled by
OE
,
are also asynchronous.
Addresses and chip enables are registered with
either address status processor (
ADSP
) or address
status controller (
ADSC
) input pins. Subsequent
burst addresses can be internally generated as
controlled by the burst advance pin (
ADV
).
Address, data inputs, and write controls are
registered on-chip to initiate self-timed WRITE
cycle. WRITE cycles can be one to eight bytes
wide
FUNCTIONAL BLOCK DIAGRAM
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
DESCRIPTION
(continued)
as controlled by the write control inputs.
Individual byte write allows individual byte to be
written.
BW1
controls
controls DQ9-DQ16.
BW3
controls DQ17-DQ24.
BW4
controls DQ25-DQ32.
DQ33-DQ40.
BW6
controls
BW7
controls DQ49-DQ56.
DQ57-DQ64.
BW1
,
BW2
,
BW3
,
BW4
,
BW5
,
BW6
,
BW7
and
BW8
can be active only with
BWE
being LOW.
GW
being LOW causes all
bytes to be written. WRITE pass-through
capability allows written data available at the output
for the immediately next READ cycle. This
device also incorporates pipelined enable circuit for
easy depth expansion without penalizing system
performance.
DQ1-DQ8.
BW2
BW5
controls
DQ41-DQ48.
BW8
controls
BYTE 4
WRITE REGISTER
ENABLE
REGISTER
BYTE 1
WRITE REGISTER
BYTE 3
WRITE REGISTER
BYTE 2
WRITE REGISTER
ADDRESS
REGISTER
DO D1 Q1
BINARY
COUNTER
& LOGIC
CLR
LOAD
Q0
BYTE 1
WRITE DRIVER
BYTE 2
WRITE DRIVER
BYTE 3
WRITE DRIVER
BYTE 4
WRITE DRIVER
16
16
14
16
A0
A1
A1'
A0'
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
INPUT
REGISTERS
8
8
8
8
8
8
8
8
64
64
64
DQ1
.
.
.
DQ64
8
A0-A15
MODE
ADV
CLK
ADSC
ADSP
BW4
BW3
BW2
BW1
CE
CE2
CE3
CE2
CE3
OE
GW
BWE
PIPELINED
ENABLE
BYTE 5
WRITE REGISTER
BYTE 6
WRITE REGISTER
BYTE 7
WRITE REGISTER
BYTE 8
WRITE REGISTER
BYTE 7
WRITE DRIVER
BYTE 8
WRITE DRIVER
BW5
BW6
BW7
BW8
8
8
8
8
BYTE 6
WRITE DRIVER
BYTE 5
WRITE DRIVER
8
8
8
8
64K x 8 x 8
MEMORY
ARRAY
Chip
Enable
Note
: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin
descriptions and timing diagrams for detailed information.
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