參數(shù)資料
型號(hào)： T35L6464A
廠商： TM Technology, Inc.
英文描述： 64K x 64 SRAM
中文描述： 64K的× 64的SRAM
文件頁(yè)數(shù)： 14/16頁(yè)
文件大?。?/td> 160K
代理商： T35L6464A
TE
CH
tm
READ/WRITE TIMING
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 14
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
A 4
High-Z
BURST RE AD
C L K
A D S C
A D S P
A D D R E S S
B W 1 - B W 8
t KC
t KH
t KL
t A DSSt A DSH
DO N'T CARE
UNDEFINED
t AS
t AH
t WS
t WH
t C ESt C EH
t DH
t K Q
tOELZ
tOEHZ
t DS
t KQ
t KQLZ
Single WR ITE
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A4+1
)
Q(A4+3)
Q(A4+2)
A5
A 3
A1
(NOTE1)
C E
( N O T E 2 )
A D V
O E
D
A 2
A6
Q
High-Z
D(A3)
D(A5)
D(A6)
Back-to-Bac k READs
Pass-through
READ
Bac k-to-Back
WRITEs
Note:
1. Q (A4) refers to output from address A4. Q (A4 + 1) refers to output from the next internal burst
address following A4.
2.
CE2
, CE2,
CE3
and CE3 have timing identical to
CE
. On this diagram, when
CE
is LOW,
CE2
,
CE3
is LOW and CE2, CE3 is HIGH. When
CE
is HIGH,
CE2
,
CE3
is HIGH and CE2,
CE3 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an
ADSP
,
ADSC
or
ADV
cycle is performed.
4.
GW
is HIGH.
5. Back-to-back READs may be controlled by either
ADSP
or
ADSC
.
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