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參數(shù)資料
| 型號： | T35L6464A-5Q |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 64 SRAM |
| 中文描述： | 64K的× 64的SRAM |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 160K |
| 代理商： | T35L6464A-5Q |
TE
CH
tm
WRITE TIMING
T35L6464A
Taiwan Memory Technology, Inc. reserves the right
P. 13
to change products or specifications without notice.
Publication Date: AUG. 1998
Revision: E
BURST WR ITE
C L K
A D S C
High-Z
A D S P
A D D R E S S
B W E ,
B W 1 - B W 8
t K C
t KH
t K L
t ADSSt ADSH
DON'T CARE
UNDEFINED
t AS
t AH
t WS
t WH
t C ESt CEH
t AA St AAH
tOEHZ
t DS
t DH
Single WRIT E
(NOTE3)
D(A1)
D(A2)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3+1)
D(A3)
A 3
A2
A1
(NOTE1)
C E
( N O T E 2 )
A D V
O E
D
ADSC extends bt ADSSt ADSH
t ADSSt ADSH
G W
t WS
t WH
D(A2+1)
D(A3+2)
BURST R EAD
Extended BURST WRITE
Q
ADV suspnds burst.
(NOTE4)
(NOTE5)
BYTE W RITE s ignals are
ignored for first c ycle when
ADSP initialtes burst.
Note:
1. Q(A2) refers to output from address A2. Q (A2 + 1) refers to output from the next internal burst address
following A2.
2.
CE2
, CE2,
CE3
and CE3 have timing identical to
CE
. On this diagram, when
CE
is LOW,
CE2
,
CE3
is LOW and CE2, CE3 is HIGH. When
CE
is HIGH,
CE2
,
CE3
is HIGH and CE2, CE3 is
LOW.
3.
OE
must be HIGH before the input data setup and hold HIGH throughout the data hold time. This prevents
input/output data contention for the time period to the byte write enable inputs being sampled.
4.
ADV
must be HIGH to permit a WRITE to the loaded address.
5. Full width WRITE can be initiated by GW LOW or GW HIGH and BWE ,BW1-BW8 LOW.
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