TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 8
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
CAPACITANCE
DESCRIPTION
Input Capacitance
Input/ Output Capacitance(DQ)
CONDITIONS
TA = 25
°
C; f = 1 MHz
VCC = 3.3V
SYM.
CI
CO
TYP
3
6
MAX
4
7
UNITS
pF
pF
NOTES
4
4
THERMAL CONSIDERATION
DESCRIPTION
CONDITIONS
Still air, soldered on 4.25x
SYM. QFP TYP UNITS
Θ
JA
20
NOTES
Thermal Resistance - Junction to
Ambient
Thermal Resistance - Junction to Case
°
C/W
1.125 inch 4-layer PCB
Θ
JB
1
°
C/W
AC ELECTRICAL CHARACTERISTICS
(Note 5) (0
°
C
≤
TA
≤
70
°
C; VCC=3.3V +10%/-5%)
DESCRIPTION
-4.5
-5
-6
-7
-8
SYM. MINMAX MINMAXMINMAXMINMAX MINMAXUNITS NOTES
Clock
Clock cycle time
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE to output valid
OE to output in Low-Z
OE to output in High-Z
Setup Times
Address
Address Status(ADSC,ADSP )tADSS 2.5
Address Advance (ADV)
Byte Write Enables
(BW1~BW4,BWE ,GW)
Data-in
tKC
tKH
tKL
8
3
3
10
4
4
12
4
4
15
5
5
20
6
6
ns
ns
ns
tKQ
tKQX
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
4.5
5
5
5
4
6
5
5
5
7
6
5
8
6
6
6
ns
ns
ns
ns
ns
ns
ns
2
2
2
3
2
3
2
3
2
3
6, 7
6, 7
9
6, 7
6, 7
4.5
4.5
0
0
0
0
0
3
6
tAS
2.5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
ns
ns
ns
ns
8, 10
8, 10
8, 10
8, 10
tAAS
tWS
2.5
2.5
tDS
tCES
2.5
2.5
3
3
3
3
3
3
3
3
ns
ns
8, 10
8, 10
Chip Enables(CE,CE2,CE2)
Hold Times
Address
Address Status(ADSC,ADSP )tADSH 0.5
Address Advance (ADV)
Byte Write Enables
(BW1~BW4,BWE ,GW)
Data-in
tAH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 10
8, 10
8, 10
8, 10
tAAH
tWH
0.5
0.5
tDH
tCEH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 10
8, 10
Chip Enables(CE,CE2,CE2)