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參數(shù)資料
| 型號(hào)： | T35L6432A-5Q |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 64K x 32 SRAM |
| 中文描述： | 64K的× 32的SRAM |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 1347K |
| 代理商： | T35L6432A-5Q |
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TE
CH
tm
T35L6432A
Taiwan Memory Technology, Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
PIN DESCRIPTIONS
QFP PINS
32-37, 44-49,
81, 82, 99, 100,
SYM.
A0-
A15
TYPE
Input-
Synchronous hold times around the rising edge of CLK. The burst counter -
generates internal addresses associated with A0 and A1,during
burst cycle and wait cycle.
Input-
Byte Write: A byte write is LOW for a WRITE cyle and HIGH for
BW2 Synchronous a READ cycle. BW1 controls DQ1-DQ8. BW2 controls DQ9-
BW3
DQ16. BW3 controls DQ17-DQ24. BW4 controls DQ25-DQ32.
BW4
Data I/O are high impedance if either of these inputs are LOW ,
conditioned by
BWE
being LOW.
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the setup and hold times around the rising edge of
CLK.
GW
Input-
Global Write: This active LOW input allows a full 32-bit WRITE
Synchronous to occur independent of the BWE and BWn lines and must meet
the setup and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip enables, write
Synchronous control and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.
CE
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device and conditions internal use of
ADSP
. This input is
sampled only when a new external address is loaded.
CE2
Input-
Synchronous Chip Enable: This active LOW input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
CE2
Input-
Synchronous Chip Enable: This active HIGH input is used to enable
Synchronous the device. This input is sampled only when a new external address
is loaded. This input can be used for memory depth expansion.
OE
Input
Output enable: This active LOW asynchronous input enables the
data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
ADSP
Input-
Address Status Processor: This active LOW input, along with
CE
Synchronous being LOW, causes a new external address to be registered and a
READ cycle is initiated using the new address.
ADSC
Input-
Address Status Controller:This active LOW input causes device to
Synchronous be deselected or selected along with new external address to be
registered. A READ or WRITE cycle is initiated depending upon
write control inputs.
DESCRIPTION
Addresses: These inputs are registered and must meet the setup and
93-96
BW1
87
88
89
98
92
97
86
83
84
85
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| T35L6432A-5T | 64K x 32 SRAM |
| T35L6432B | 64K x 32 SRAM |
| T35L6432B-10Q | 64K x 32 SRAM |
| T35L6432B-12T | 64K x 32 SRAM |
| T35L6464A | 64K x 64 SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| T35L6432A-5T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-10Q | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6432B-12T | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 32 SRAM |
| T35L6464A | 制造商:TMT 制造商全稱:TMT 功能描述:64K x 64 SRAM |
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