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參數(shù)資料
| 型號： | T15V4M16A-70C |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 256K X 16 LOW POWER CMOS STATIC RAM |
| 中文描述： | 256 × 16低功耗CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 90K |
| 代理商： | T15V4M16A-70C |
TE
CH
tm
WRITE CYCLE 3
(
UB
,
LB
Controlled)
Preliminary T15V4M16A
Taiwan Memory Technology, Inc. reserves the right
P. 9
to change products or specifications without notice.
Publication Date: SEP. 2000
Revision:0.B
NOTES ( WRITE CYCLE ) :
1. A write occurs during the overlap of a low
CE
, a low WE. A write begins at the lateat transition
among
CE
goes low, WEgoing low. A write end at the earliest transition among
CE
going
high, WE going high.
t
WP
is measured from the beginning of write to the end of write.
2.
t
CW
is measured from the later of
CE
going low to the end of write.
3.
t
AS
is measured from the address valid to the beginning of write.
4.
t
WR
is measured from the end of write to the address change.
DO N'T CARE
UNDEFINE D
tWC
tDW
DI N
tDH
tWR
tAS
tWP
tCW
A dd re s s
C E
W E
DO U T
U B / L B
tAW
High-Z
High-Z
High-Z
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