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參數(shù)資料
| 型號(hào)： | T15V4M16A-70C |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 256K X 16 LOW POWER CMOS STATIC RAM |
| 中文描述： | 256 × 16低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 90K |
| 代理商： | T15V4M16A-70C |
TE
CH
tm
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled,
CE
=
OE
=
Preliminary T15V4M16A
Taiwan Memory Technology, Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: SEP. 2000
Revision:0.B
IL
V
,
WE
=
V
IH
,
LB
or/and
UB
=
tRC
IL
V
)
READ CYCLE 2 (
WE
=
V
IH
)
DON'T CARE
UNDEFINED
C E
t
OE
U B / L B
t
BA
t
OHZ
D
OUT
O E
t
RC
t
ACE
t
AA
t
OLZ
t
BLZ
t
LZ
High-Z
t
BHZ
t
HZ
t
OH
A d d r e s s
(Chip Enable Controlled)
Notes (READ CYCLE) :
1.
WE
are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to
V
OH
or V
OL
levels.
4. At any given temperature and voltage condition. t
HZ
(max.) is less than t
LZ
(min.) both for a given device
and from device to device interconnection.
5. Transition is measured
±
200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
6. Device is continuously selected with
CE
=V
IL
.
Address
tOH
tAA
DOUT
Previous Data Valid
Data Valid
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