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參數(shù)資料
| 型號(hào)： | T15V4M08A-70P |
| 廠商： | TM Technology, Inc. |
| 英文描述： | 512K X 8 LOW POWER CMOS STATIC RAM |
| 中文描述： | 為512k × 8低功耗CMOS靜態(tài)RAM |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | T15V4M08A-70P |
TE
CH
tm
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled,
CE
=
OE
=
Preliminary T15V4M08A
Taiwan Memory Technology, Inc. reserves the right
P. 7
to change products or specifications without notice.
Publication Date: MAR. 2001
Revision:0.A
IL
V
,
WE
=
V
IH
)
READ CYCLE 2 (
WE
=
V
IH
)
t
R C
t
A A
t
A C E
t
O E
t
O L Z
t
L Z
t
O H Z
t
H Z
t
O H
A d d r e s s
C E
O E
D
O U T
H i g h - Z
D O N ' T C A R E
U N D E F I N E D
Notes : (READ CYCLE) :
1.
WE
are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to
V
OH
or V
OL
levels.
4. At any given temperature and voltage condition. t
HZ
(max.) is less than t
LZ
(min.) both for a given device
and from device to device interconnection.
5. Transition is measured
±
200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
6. Device is continuously selected with
CE
=V
IL
.
tRC
Ad dres s
tOH
tAA
DOUT
Previous Data Valid
Data Valid
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