參數(shù)資料
型號(hào): STW81100AT
廠商: 意法半導(dǎo)體
英文描述: MULTI-BAND RF FREQUENCY SYNTHESIZER WITH INTEGRATED VCOS
中文描述: 多波段射頻頻率合成器帶有集成的VCO
文件頁(yè)數(shù): 16/23頁(yè)
文件大?。?/td> 915K
代理商: STW81100AT
STW81100
16/23
Table 10.
8.1.8 Multi-byte write mode
The multi-byte write mode can start from any internal address. The master sends the data bytes and each
one is acknowledged. The master terminates the transfer by generating a STOP condition.
The sub-address decides the starting byte. A multi byte with sub-address 07H and 5 DATA_IN byte would
affect the bytes starting from DATA_OUT[63:56] to DATA_OUT[31:24] and so on.
Table 11.
8.1.9 Current Byte Address Read
In the current byte address read mode, following a START condition, the master sends the device address
with the rw bit set to 1 (No sub-address is needed as there is only 1 byte read register). The STW81100
acknowledges this and outputs the data byte. The master does not acknowledge the received byte, but
terminates the transfer with a STOP condition.
Table 12.
8.2 Timing Specification
Figure 20. Data and clock
Table 13.
S
1100A
2
A
1
A
0
0
ack
sub-address byte
ack
DATA IN
ack
P
S
1100A
2
A
1
A
0
0
ack
sub-address byte
ack
DATA IN
ack
....
DATA IN
ack
P
S
1100A
2
A
1
A
0
0
ack
sub-address byte
ack
DATA IN
ack
....
DATA IN
ack
P
Symbol
T
cs
T
ch
T
cwh
T
cwl
Parameter
Minimum time (ns)
2
2
10
5
Data to clock set up time
Data to clock hold time
Clock pulse width high
Clock pulse width low
t
cs
t
ch
t
cwh
t
cwl
SDA
SCL
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