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參數(shù)資料
| 型號(hào)： | STV2001 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | I2C SINGLE FREQUENCY DEFLECTION PROCESSOR AND 120 MHz RGB PREAMPLIFIER |
| 中文描述： | 撓度的I2C單頻處理器和120兆赫的RGB前置放大器 |
| 文件頁數(shù)： | 27/46頁 |
| 文件大小： | 528K |
| 代理商： | STV2001 |
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STV2001
27/
46
14.2.3 - PLL2
PLL2 ensures a constant position of the shaped
flyback signal in comparison with the sawtooth of
the VCO, taking into account the saturation time
Ts (see
Figure 10
).
Figure 10. PLL2 Timing Diagram
The phase comparator of PLL2 (phase type com-
parator) is followed by a charge pump (typical out-
put current: 0.5 mA).
VBCAP pin is used to filter noise on PLL2 top com-
parator via an external capacitor.
The flyback input consists of an NPN transistor.
This input must be current driven. The maximum
recommended
input
(see
Figure 11
).
current
is
5 mA
Figure 11. Flyback Input Electrical Diagram
The duty cycle is fixed at 55%. For a safe start-up
operation, the initial duty cycle (after power-on re-
set) is 85% in order to avoid having too long a con-
duction period of the horizontal scanning transis-
tor.
The maximum storage time (Ts Max.) is :
0.44T
H
- T
FLY
/2).
Typically, T
FLY
/T
H
corresponds to around 20 %
which means that Ts max represents approxim
tively 34 % of T
H
.
14.2.4 - Output Section
The H-drive signal is sent to the output through a
shaping stage which also controls the fixed H-
drive duty cycle (see
Figure 10
). In order to secure
the scanning power part operation, the output is in-
hibited in the following cases :
-when V
CC
is too low,
-when the ABL protection is activated,
-during the Horizontal flyback,
-when the HDrive I
2
C bit control is off.
The output stage consists of a NPN bipolar tran-
sistor. Only the collector is accessible
(see
Figure 12
). Emitter is connected directly to a
separate ground pin.
Figure 12.
This output stage is intended for "reverse" base
control, where setting the output NPN in off-state
will control the power scanning transistor in off-
state.
The maximum output current is 15 mA, and the
corresponding voltage drop of the output V
CEsat
is
0.4 V Max.
Obviously, the power scanning transistor cannot
be directly driven by the integrated circuit. An inter-
face either bipolar or MOS type has to be added
between the circuit and the power transistor.
H Osc
Sawtooth
H Drive
1.6V
4.0V
6.4V
7/8T
H
1/8T
H
Ts
Duty Cycle
Internally
Shaped Flyback
Flyback
400
HFLY
36
Q1
GND 0V
20k
34
V
CC
Hout
33 HDGND
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