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參數(shù)資料
| 型號： | STV0056A |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Satellite Sound and Video Processor(衛(wèi)星探測和視頻處理器) |
| 中文描述： | 衛(wèi)星聲音和視頻處理器（衛(wèi)星探測和視頻處理器） |
| 文件頁數(shù)： | 17/26頁 |
| 文件大?。?/td> | 247K |
| 代理商： | STV0056A |
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I
2
C PROTOCOL
1) WRITING
to the chip
S
-Start Condition
P
-StopCondition
CHIP ADDR
- 7 bits.Programmable06H or 46H(STV0056Aonly) with Pin HA.
W
-Write/Read bit is the 8th bit of thechip address.
A
-ACKNOWLEDGEafter receiving8 bitsof data/adress.
REG ADDR
Address of register to be writtento, 8 bits of which bits 3, 4, 5, 6 & 7 are ’X’ or
don’t care ie only the first 3 bits are used
DATA
8 bitsof databeingwritten totheregister. All8 bitsmustbe written to atthe same
time.
REG ADDR/A/DATA/A
can be repeated, the write process can continue untill terminated with a STOP
condition. If the
REGADDR
is higher than 07 then IIC PROTOCOL will still be
met (ie an
A
generated).
Example :
S
06
W
A
00
A
55
A
01
A
8F
A
P
2) READING
from the chip
When reading,thereisanauto-incrementfeature.Thismeans anyreadcommandalwaysstartsby reading
Reg 8 and will continue to read the following registersin orderafter eachacknowledgeor until there is no
acknowledge or a stop. This function is cyclic that is it will read the same set of registers without
re-addressingthe chip. There are two modes of operation as set by writing to bit 7 of register 0. Read 3
registersin a cyclic fashionor all 5 registers in a cyclic fashion. Note only the last 5 of the 11registers can
be read.
Reg0 bit 7 =L
Start / chipadd / R / A/ Reg8 / A/ Reg9 / A/ Reg 0A/ A/ Reg8 / A/ Reg9 /A / Reg 0A
/... / P /
Reg0 bit 7 =H
Start / chip add / R / A/ Reg8 /A / Reg 9 / A/ Reg0A / A/ Reg 7 / A/ Reg 6 / A/ Reg 8
/ A/ Reg 9 / A/ Reg 0A / A/ Reg7 / A/ Reg 6 / ... / P /
CONTROL REGISTERS
Reg 0
Bit (default 00
HEX
)
0
L
Select 5 bits audio volume control
1
L
Select 5 bits audio volume control
2
L
Select 5 bits audio volume control
3
L
Select 5 bits audio volume control
4
L
Select 5 bits audio volume control
5
L
Audio mux switch K4 - ANRS I/P select (L = PLL)
6
L
Audio mux switch K3 - ANRSselect (L= no ANRS, H = ANRS)
7
L
L = read 3 registers, H = read 5 registers
write only
00H = MUTE
01H = -26.75dB
: : : :
1.25dBsteps up to
1FH = +12dB
:
Reg 1
Bit (default 00
HEX
)
0
L
Select video gain bits
1
L
Select video gain bits
2
L
Select video gain bits
3
L
Select video gain bits
4
L
Select video gain bits
5
L
Select video gain bits
6
L
Selected video invert (H= inverted,L = non inverted)
7
L
Videodeemphasis 1 / Video deemphasis2 (L: V
ID
De-em1)
write only
00H = 0dB
01H = +0.202dB
02H = +0.404dB
n
= + 0.202 dB * n
3FH = + 12.73 dB
STV0056A
17/26
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