參數(shù)資料
型號(hào): STPCI2HDYC
廠商: STMICROELECTRONICS
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA516
封裝: PLASTIC, BGA-516
文件頁數(shù): 53/109頁
文件大?。?/td> 2430K
代理商: STPCI2HDYC
STPC ATLAS
48/109
Issue 1.1 - March 23, 2004
Note: Refer to Figure 4-1.
4.5.1. POWER ON SEQUENCE
Figure 4-3 describes the power-on sequence of
the STPC, also called cold reset.
There is no dependency between the different
power supplies and there is no constraint on their
rising time.
SYSRSTI# as no constraint on its rising edge but
must stay active until power supplies are all within
specifications,
a
margin
of
10
s is even
recommended to let the STPC PLLs and strap
options stabilize.
Strap Options are continuously sampled during
SYSRSTI# low and must remain stable. Once
SYSRSTI# is high, they MUST NOT CHANGE
until SYSRSTO# goes high.
Bus activity starts only few clock cycles after the
release of SYSRSTO#. The toggling signals
depend on the STPC configuration.
In ISA mode, activity is visible on PCI prior to the
ISA bus as the controller is part of the south
bridge.
In Local Bus mode, the PCI bus is not accessed
and the Flash Chip Select is the control signal to
monitor.
Table 4-9. Drive Level and Measurement Points for Switching Characteristics
Symbol
Value
Units
VREF
1.5
V
VIHD
2.5
V
VILD
0.0
V
Figure 4-1. Drive Level and Measurement Points for Switching Characteristics
CLK:
VRef
VILD
VIHD
Tx
LEGEND:
A - Maximum Output Delay Specification
B - Minimum Output Delay Specification
C - Minimum Input Setup Specification
D - Minimum Input Hold Specification
VRef
Valid
OUTPUTS:
INPUTS:
Output n
Output n+1
Input
MAX
MIN
A
B
CD
VRef
VILD
VIHD
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