參數(shù)資料
型號： STPCI2HDYC
廠商： STMICROELECTRONICS
元件分類： 外設及接口
英文描述： MULTIFUNCTION PERIPHERAL, PBGA516
封裝： PLASTIC, BGA-516
文件頁數(shù)： 28/109頁
文件大?。?/td> 2430K
代理商： STPCI2HDYC
STPC ATLAS
Issue 1.1 - March 23, 2004
25/109
IRQ_MUX[3:0] Multiplexed Interrupt Request.
These are the ISA bus interrupt signals. They are
to be encoded before connection to the STPC
Atlas using ISACLK and ISACLKX2 as the input
selection strobes.
Note
that
IRQ8B,
which
by
convention
is
connected to the RTC, is inverted before being
sent to the interrupt controller, so that it may be
connected directly to the IRQ# pin of the RTC.
ISAOE# Bidirectional OE Control. This signal
controls the OE signal of the external transceiver
that connects the IDE DD bus and ISA SA bus.
KBCS# Keyboard Chip Select. This signal is
asserted if a keyboard access is decoded during a
I/O cycle.
ZWS#
Zero Wait State. This signal, when
asserted by addressed device, indicates that
current cycle can be shortened.
DACK_ENC[2:0] DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
encoded by the STPC Atlas before output and
should be decoded externally using ISACLK and
ISACLKX2 as the control strobes.
DREQ_MUX[1:0] ISA Bus
Multiplexed
DMA
Request. These are the ISA bus DMA request
signals.
They
are
to
be
encoded
before
connection to the STPC Atlas using ISACLK and
ISACLKX2 as the input selection strobes.
TC ISA Terminal Count. This is the terminal count
output of the DMA controller and is connected to
the TC line of the ISA bus. It is asserted during the
last DMA transfer, when the Byte count expires.
2.2.5. PCMCIA INTERFACE
RESET Card Reset. This output forces a hard
reset to a PC Card.
A[25:0] Address Bus. These are the 25 low bits of
the system address bus of the PCMCIA bus.
These pins are used as an input when an PCMCIA
bus owns the bus and are outputs at all other
times.
D[15:0] I/O Data Bus (PCMCIA). These are the
external PCMCIA databus pins.
IORD# I/O Read. This output is used with REG# to
gate I/O read data from the PC Card, (only when
REG# is asserted).
IOWR# I/O Write. This output is used with REG#
to gate I/O write data from the PC Card, (only
when REG# is asserted).
WP Write Protect. This input indicates the status
of the Write Protect switch (if fitted) on memory PC
Cards (asserted when the switch is set to write
protect).
BVD1, BVD2 Battery
Voltage Detect. These
inputs will be generated by memory PC Cards that
include batteries and are an indication of the
condition of the batteries. BVD1 and BVD2 are
kept asserted high when the battery is in good
condition.
READY#/BUSY#/IREQ#
Ready/busy/Interrupt
request. This input is driven low by memory PC
Cards to signal that their circuits are busy
processing a previous write command.
WAIT# Bus Cycle Wait. This input is driven by the
PC Card to delay completion of the memory or I/O
cycle in progress.
OE# Output Enable. OE# is an active low output
which is driven to the PC Card to gate Memory
Read data from memory PC Cards.
WE#/PRGM# Write Enable. This output is used by
the host for gating Memory Write data. WE# is
also used for memory PC Cards that have
programmable memory.
REG# Attribute Memory Select. This output is
inactive (high) for all normal accesses to the Main
Memory of the PC Card. I/O PC Cards will only
respond to IORD# or IOWR# when REG# is active
(low). Also see Section 2.2.7.
CD1#, CD2# Card Detect. These inputs provide
for the detection of correct card insertion. CD#1
and CD#2 are positioned at opposite ends of the
connector to assist in the detection process.
These inputs are internally grounded on the PC
Card therefore they will be forced low whenever a
card is inserted in a socket.
CE1#, CE2# Card Enable. These are active low
output signals provided from the PCIC. CE#1
enables even Bytes, CE#2 odd Bytes.
ENABLE# Enable. This output is used to activate/
select a PC Card socket. ENABLE# controls the
external address buffer logic.C card has been
detected (CD#1 and CD#2 = '0').
ENIF# ENIF. This output is used to activate/select
a PC Card socket.
EXT_DIR EXternal Transceiver Direction Control.
This output is high during a read and low during a
write. The default power up condition is write
(low). Used for both Low and High Bytes of the
Data Bus.
VCC_EN#, VPP1_EN0, VPP1_EN1, VPP 2_EN0,
VPP2_EN1 Power Control. Five output signals
相關PDF資料
PDF描述
STPIC6C595M 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16
STR710RZT6 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQFP144
STUF32864EHLFT SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
STV3208CV 9-BIT, DSP-FAST COSINE TRANSFRM PROCESSOR, PQFP44
STVA16857AGLF SSTV SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO48
相關代理商/技術參數(shù)
參數(shù)描述
STPCI2HEYC 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCI2HEYI 功能描述:微處理器 - MPU 133MHz x86 SoC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324
STPCINDUSTRIAL 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:PC Compatible Embedded Microprocessor
STP-CN04 功能描述:烙鐵 Cartridge Conical 0.4mm (0.016in) RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
STP-CN05 功能描述:烙鐵 Cartridge Conical 0.5mm (0.02in) RoHS:否 制造商:Weller 產(chǎn)品:Soldering Stations 類型:Digital, Iron, Stand, Cleaner 瓦特:50 W 最大溫度:+ 850 F 電纜類型:US Cord Included
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*