參數(shù)資料
型號： STM8L162R8T6
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, LQFP-64
文件頁數(shù)： 74/116頁
文件大?。?/td> 1229K
代理商： STM8L162R8T6
Option bytes
STM8L162R8, STM8L162M8
54/123
Doc ID 17959 Rev 1
Table 12.
Option byte description
Option
byte
No.
Option description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in the STM8L reference manual (RM0031).
OPT1
UBC[7:0] Size of the user boot code area
UBC[7:0] Size of the user boot code area
0x00: No UBC
0x01: Page 0 reserved for the UBC and write protected.
0xFF: Page 0 to 254 reserved for the UBC and write-protected.
Refer to User boot code section in the STM8L reference manual (RM0031).
OPT2
PCODESIZE[7:0] Size of the proprietary code area
0x00: No proprietary code area
0x01: Page 0 reserved for the proprietary code and read/write protected.
0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected.
Refer to Proprietary code area (PCODE) section in the STM8L reference manual (RM0031) for more
details.
OPT3
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent window watchdog reset on Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
OPT4
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
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