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參數(shù)資料
| 型號： | STM8L162R8T6 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, LQFP-64 |
| 文件頁數(shù)： | 24/116頁 |
| 文件大小： | 1229K |
| 代理商： | STM8L162R8T6 |
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STM8L162R8, STM8L162M8
Functional overview
Doc ID 17959 Rev 1
9/110
corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3/VDD4
must not be left unconnected.
●
VSSA, VDDA = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must be
connected to VDD and VSS, respectively.
●
VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
●
VREF+ (for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
externally through VREF+.
3.3.2
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. When the microcontroller operates
between 1.8 and 3.6 V, BOR is always active and ensures proper operation starting from
1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts,
either to confirm or modify default thresholds, or to disable BOR permanently (in which
case, the VDD min value at power-down is 1.65 V).
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Halt mode, it is possible to automatically switch off the
internal reference voltage (and consequently the BOR) in Halt mode. The device remains in
reset state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for
any external reset circuit.
Note:
When the microcontroller operates between 1.65 and 3.6 V, BOR is permanently disabled.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The high density STM8L162xx devices embed an internal voltage regulator for generating
the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
●
Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
●
Low power voltage regulator mode (LPVR) for Halt, Active-halt, Low power run and Low
power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4
Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
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