參數(shù)資料
型號: STM8AH5199TAU
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64
封裝: 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件頁數(shù): 99/112頁
文件大小: 2161K
代理商: STM8AH5199TAU
STM8AF61xx, STM8AH61xx, STM8AF51xx, STM8AH51xx
Electrical characteristics
Doc ID 14395 Rev 5
11.3.8
SPI interface
Unless otherwise specified, the parameters given in Table 54 are derived from tests
performed under ambient temperature, fMASTER frequency, and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 54.
SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
0
10
MHz
Slave mode
VDD < 4.5 V
0
6(1)
VDD = 4.5 V to 5.5 V
0
tr(SCK)
tf(SCK)
SPI clock rise and fall time Capacitive load: C = 30 pF
25(2)
ns
tsu(NSS)
(3)
NSS setup time
Slave mode
4 * tMASTER
th(NSS)
NSS hold time
Slave mode
70
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
110
140
tsu(MI)
tsu(SI)
Data input setup time
Master mode
5
Slave mode
5
th(MI)
th(SI)
Data input hold time
Master mode
7
Slave mode
10
ta(SO)
Data output access time
Slave mode
3* tMASTER
tdis(SO)
(3)(5) Data output disable time
Slave mode
25
tv(SO)
Data output valid time
Slave mode
(after enable edge)
VDD < 4.5 V
75
VDD = 4.5 V to 5.5 V
53
tv(MO)
Data output valid time
Master mode (after enable edge)
30
th(SO)
Data output hold time
Slave mode (after enable edge)
31
Master mode (after enable edge)
12
1.
fMAX is fMASTER/2.
2.
The pad has to be configured accordingly (fast mode).
3.
Values based on design simulation and/or characterization results, and not tested in production.
4.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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