參數(shù)資料
型號(hào)： STLC2500
廠商： 意法半導(dǎo)體
英文描述： BLUETOOTH⑩ SINGLE CHIP
中文描述： 單芯片藍(lán)牙⑩
文件頁(yè)數(shù)： 3/23頁(yè)
文件大?。?/td> 241K
代理商： STLC2500
3/23
STLC2500
3.4
The STLC2500 supports, on the same input pin, the system clock both as a sine wave clock and as a dig-
ital clock (see table 15 for selection). The system clock section is powered by VDD_CLD (G08 and H09).
The voltage range for VDD_CLD is the same as for VDD_IO_A.
Clock specifications
Table 6. System clock supported frequencies
Table 7. System clock overall specifications
Table 8. System clock, sine wave specifications
Table 9. System clock, digital clock DC specifications
Table 10. System clock, digital clock AC specifications
Table 11. Low Power clock specifications
The low power clock pin is powered by connecting VDD_IO_B to the wanted supply.
Symbol
F
IN
Parameter
Values
Unit
MHz
Clock input frequency list
13, 26, 19.2, 38.4
Symbol
F
INTOL
Parameter
Min.
-20
Typ.
Max.
20
Unit
ppm
Tolerance on input frequency
Symbol
V
PP
N
H
Z
INRe
Parameter
Min.
0.2
Typ.
0.5
Max.
1
-25
90
Unit
V
dBc
K
Peak to peak voltage range
Total harmonic content of input signal
Real part of parallel input impedance at pin
30
60
Symbol
V
IL
Parameter
Min.
Typ.
Max.
0.22 *
VDD_IO_A
Unit
V
Low Level input voltage
V
IH
High Level input voltage
0.85 *
VDD_IO_A
V
Symbol
T
RISE
T
FALL
D
CYCLE
Parameter
Min.
Typ.
1,5
1,5
Max.
6
6
Unit
ns
ns
10%-90% rise time
90%-10% fall time
Duty Cycle
45
50
55
%
Symbol
Parameter
Min.
30
Typ.
Max.
70
±
250
Unit
%
ppm
Duty Cycle
Accuracy
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