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參數(shù)資料
| 型號： | STFLWARP11PL |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | WEIGHT ASSOCIATIVE RULE PROCESSOR |
| 中文描述： | 重量的聯(lián)想規(guī)則處理器 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 215K |
| 代理商： | STFLWARP11PL |
W.A.R.P. TIMING TABLES
Off-line Phase Timing (Internal RAMs Loading withCharge Mode ”0”)
O F L
I0 -I6
D ATA0
D ATA n
DATA 1
M C LK
F IN
N P
E P
F IN d e te c tion
DATA0 a cq uis ition
DATA1 a cq uis ition
DATAn a c q uis ition
T
AC Q
T
AC Q =
2 0 0 n s fo r a c o n fig ura tio n with 1 6 in p u ts , 8 o u tp uts , 2 8 ru le s
Timing Table Description:
OFF-LINEphase (CHM ”0”)
- CHM [INPUT] low will enablethe ’manualdownloading’by specifyingthe address anddata to be loaded
into W.A.R.P..
- MCLK [INPUT] mustbe connectedwith the externalsynchronizationsignal.
- PRST[INPUT] must be sethigh to enable the device.
- OFL[INPUT]mustbesethightoenabletheconfigurationloadingphaseintotheinternalRAMsofW.A.R.P..
- The inputto be written into the internal memories at the addressspecifiedin A0-A9 mustbe put into I0-I7
bus .
- SYNC [OUTPUT] will be provided to synchronize input data (I0-I7,A0-A9) coming from an external
database.SYNC frequency is MCLK/32 with a phase delay of t
CSP
ns . W.A.R.P. stores the data present
on inputbuses at the rising edge of MCLK, returns a SYNC pulse after t
CSP
ns indicatingthat is waiting for
new dataandaddress thatmustbe givenwithin next31MCLKpulses. Afterwards W.A.R.P. stores thedata
on inputbuses and restoresa new SYNCpulse.
W.A.R.P.stores the data situated in I0-I7 andthe addressesA0-A9into its internal registers.
Figure 8.
Block Diagram for W.A.R.P. downloading (CHM ”0”)
11/19
W.A.R.P.1.1
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