- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380764 > STFLWARP11PG (意法半導(dǎo)體) Circular Connector; No. of Contacts:3; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:16-7 RoHS Compliant: No PDF資料下載
參數(shù)資料
| 型號(hào)： | STFLWARP11PG |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:16-7 RoHS Compliant: No |
| 中文描述： | 重量的聯(lián)想規(guī)則處理器 |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大小： | 215K |
| 代理商： | STFLWARP11PG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)當(dāng)前第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)
On-line Phase Timing (Output Generation) Working Frequency 40MHz
O0-O9
MCLK
NP
EP
end of
computation
OCNT0-3
STB
start of
computation
data output
storag e
data output
storag e
last output data
OUT NUMn-1
last output number
NEW DATA
ACQUISITION
DATAOUT 1
data output
storage
T
comp=
600 ns(first process, pipeline empty), 310 ns (next processes) for a configurationwith 16inputs, 8 outputs, 28 rules
Elapsed time from the first data acquisition to the first output: 810 nsfor the first cycle , 525ns forthe other ones
.
T
COMP
OUT NUM1
OUT NUM2
DATAOUT n-1
DATAOUT 2
T
COMP
T
COMP
T
COMP
Timing Table Description
: ON-LINE phase
2
nd
step:Elaboration
- MCLK [INPUT] must be connectedwith the externalsynchronization signal.
- OFL[INPUT] must remain low during this phase.
- NP [OUTPUT] remains highduring this phase.
- EP [OUTPUT] is set high during this phase.
- STB [OUTPUT] is set high for a clock period every time an output value has been calculated. It informs
that it is possible to utilizethe outputwhich is situated in the output bus (O0-O9).The STB pulse starts at
the rising edgeof the MCLKand stops at the next rising edge of the MCLK. At thefalling edge of the STB
the data situated on the O0-O9bus can be stored.
- The current output on the O0-O9 [OUTPUT] bus is provided exactly when the STB signal rises and it
doesnot change until a new STBsignal occurs.
- Theoutput identifieron theOCNT0-OCNT3 [OUTPUT] bus isprovided exactlywhenthe STB signalrises
and it does not change until a new STBsignal occurs.
- NP [OUTPUT] is set low whenthe penultimate STROBE is disabled allowing a newacquisition phase to
start while W.A.R.P.is still elaboratingthe last output.
- When the last outputhas been provided, EP will be automaticallyset low.
14/19
W.A.R.P.1.1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| STFLWARP11PG-PL | AB 3C 1#8 2#16 SKT RECP |
| STFLWARP20L | ADAPTIVE FUZZY MODELLER |
| STFLAFM10 | ADAPTIVE FUZZY MODELLER |
| STFLAFM10SW | ADAPTIVE FUZZY MODELLER |
| STFLSTUDIO2KIT | Silver Mica Capacitor; Capacitance:6200pF; Capacitance Tolerance:+/- 5%; Series:CD30; Voltage Rating:500VDC; Capacitor Dielectric Material:Mica; Termination:Radial Leaded; Lead Pitch:11.1mm; Leaded Process Compatible:No RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| STFLWARP11PG-PL | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADAPTIVE FUZZY MODELLER |
| STFLWARP11PL | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:WEIGHT ASSOCIATIVE RULE PROCESSOR |
| STFLWARP20 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT FUZZY CO-PROCESSOR |
| STFLWARP20/PL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| STFLWARP20L | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADAPTIVE FUZZY MODELLER |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。