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參數(shù)資料
| 型號： | STFLWARP11PG |
| 廠商： | 意法半導體 |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:16-7 RoHS Compliant: No |
| 中文描述： | 重量的聯(lián)想規(guī)則處理器 |
| 文件頁數(shù)： | 12/19頁 |
| 文件大?。?/td> | 215K |
| 代理商： | STFLWARP11PG |
Off-line Phase Timing (Internal RAMs Loading withCharge Mode ”1”)
DC LK
OF L
I0-I7
E PA0-E PA2 +
A0-A9
AD DRE S S 0
ADDRE S S 1
AD DRE S S n
MC LK
DATA0
DATAn
DATA1
W.A.R .P. store s DATA0
W.A.R.P. store s DATA1
W.A.R .P. store s DATAn
P RS T
CHM
S YNC
Timing Table Description:
OFF-LINEphase (CHM ”1”)
- CHM [INPUT] high will enable the ’automatic downloading’, specifying the address of the non-volatile
memory where are data to be loaded into W.A.R.P.. Internal memory addresses are automatically
generated.
- MCLK [INPUT] must be connectedwith the externalsynchronizationsignal.
- PRST [INPUT] must be set high to enable the device.
- OFL[INPUT] must be set high to enablethe loadingphase of datainto the internalRAMs of W.A.R.P..
- SYNC [OUTPUT] will be provided to synchronizeinput data (I0-I7) coming from the external database.
SYNC frequencyis MCLK/32.
- DCLK[INTERNAL] setstheworkingfrequencyaccordingto theOFLcontrolsignal.Itdrives theaddressing
ofdatacoming fromthe externalmemory supportbythe I0-I7 inputbus. The externalmemory supportmust
return the data (addressedby EPA0-EPA2+A0-A9[OUTPUT]) into I0-I7 in a periodof time no longerthan
half a period of DCLK. DCLK frequencyis MCLK/32.
Figure 9.
Block Diagram for W.A.R.P. downloading (CHM ”1”)
12/19
W.A.R.P.1.1
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