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參數(shù)資料
| 型號(hào)： | STFLWARP11PG |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:3; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:16; Circular Contact Gender:Pin; Circular Shell Style:Cable Receptacle; Insert Arrangement:16-7 RoHS Compliant: No |
| 中文描述： | 重量的聯(lián)想規(guī)則處理器 |
| 文件頁(yè)數(shù)： | 13/19頁(yè) |
| 文件大?。?/td> | 215K |
| 代理商： | STFLWARP11PG |
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On-line Phase Timing(Acquisition and Elaboration) Working Frequency 40MHz
OFL
I0-I6
DATA0
DATAn
DATA1
MCLK
FIN
NP
EP
FIN detection
DATA0 acquisition
DATA1 acquisition
DATAn acquisition
T
ACQ
T
ACQ =
200 ns for a configuration with 16 inputs, 8 outputs, 28 rules
Timing Table Description:
ON-LINE phase
1
st
step:Acquisition
- MCLK[INPUT] must be connectedwith the externalsynchronization signal.
- OFL[INPUT] must be set low to enable the acquisition/elaborationphase of W.A.R.P..
- FIN [INPUT] must be sethigh for at least 1clock period to start the acquisitionphase. OFLmust already
be low since at least 4 clock periods before providing a FIN pulse. FIN duration must be in the range
[1clock,2clockperiods]. FIN pulse mustn’t coincide with NP transitions.
- NP [OUTPUT] will remain low during the acquisitionphase.
- Theinput data must be sent toI0-I6 after OFL hasbeen set lowandFIN has beensethigh. Datasituated
in I0-I6 arestored into its internalregisters at each next rising edge of the MCLK.
- After the current inputs have been acquired, the NP [OUTPUT] high signal informs that the elaboration
phase can start. Thisinformation is provided thanks to the configurationstored in the programmemory.
Figure 10. Input/Output Connection Block Diagram
13/19
W.A.R.P.1.1
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相關(guān)代理商/技術(shù)參數(shù) |
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| STFLWARP20/PL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| STFLWARP20L | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:ADAPTIVE FUZZY MODELLER |
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