參數(shù)資料
型號(hào): STE2001DIE2
廠商: 意法半導(dǎo)體
英文描述: 65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER
中文描述: 65 × 128單芯片LCD控制器/驅(qū)動(dòng)
文件頁數(shù): 21/36頁
文件大小: 326K
代理商: STE2001DIE2
21/36
STE2001
ParallelInterface
The STE2001 parallel Interface is a unidirectional link between the display driverand the application supervisor.
It consists of ten lines: eight data lines (from DB7 to DB0) and two control lines. The control lines are: enable
(E) for data latch and PD/C for mode selection.
The data lines and the control line values are internally latched on E rising edge (fig. 23).
Figure 23. Parallel interface timing
Table 1. Instruction Set
Instruction
D/C
R/W
Description
B7
B6
B5
B4
B3
B2
B1
B0
H=0 or H=1
NOP
0
0
0
0
0
0
0
0
0
0
No Operation
Function Set
0
0
0
0
1
MX
MY
PD
V
H
PowerDown Management; Entry
Mode; Extended Instruction Set
Read Status Byte
0
1
PD
TRS
BRS
D
E
MX
MY
DO
( I
2
C interface only )
Write Data
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Writes data to RAM
H=0
Memory Blank
0
0
0
0
0
0
0
0
0
1
Starts Memory Blank Procedure
Scroll
0
0
0
0
0
0
0
0
1
DIR
Scrolls by one RowUP or DOWN
V
LCD
Range Setting
0
0
0
0
0
0
0
1
0
PRS
V
LDC
programmingrangeselection
Display Control
0
0
0
0
0
0
1
D
0
E
Select Display Configuration
Set CP Factor
0
0
0
0
0
1
0
0
S1
S0
ChargePump Multiplication Facto
r
Set RAM Y
0
0
0
1
0
0
Y3
Y2
Y1
Y0
Set Horizontal (Y) RAM Address
Set RAM X
0
0
1
X6
X5
X4
X3
X2
X1
X0
Set Vertical (X) RAM Address
H=1
Checker Board
0
0
0
0
0
0
0
0
0
1
Starts Checker Board Procedure
Multiplex Select
0
0
0
0
0
0
0
0
1
MUX
Selects MUX factor
TC Select
0
0
0
0
0
0
0
1
TC1 TC0
Set TemperatureCoefficientforV
LDC
Output Address
0
0
0
0
0
0
1
DO
TRS
BRS
Set Row Order on Output Pads
Bias Ratios
0
0
0
0
0
1
0
BS2
BS1 BS0
Set desired Bias Ratios
Reserved
0
0
0
1
X
X
X
X
X
X
Not to be used
Set V
OP
0
0
1
OP6
OP5
OP4
OP3
OP2
OP1
OP0
V
OP
register Write instruction
PD/C
t
SU(A)
t
SU(D)
DB0-DB7
E
D00IN1162
t
W(en)
t
HO(D)
t
CY(en)
t
h(A)
RES
t
START
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